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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V3640L6BBG8 Renesas Electronics	1	FIFO 1K x 36 SuperSync II FIFO, 3.3V	BGA	72V3640L6BBG8	3D model available Symbol and footprint available 3	1 Download Model
	SN74V273-10PZA Texas Instruments	1	FIFO 16384 x 18 Synch FIFO Memory	Quad Flat Packages	SN74V273-10PZA	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7811-20FN Texas Instruments	1	IC SYNC FIFO MEM 1024X18 68-PLCC	Plastic Leaded Chip Carrier	SN74ACT7811-20FN	3D model available Symbol and footprint available 3	1 Download Model
	SN74V3640-7PEU Texas Instruments	1	FIFO 1024 x 36 Synch FIFO Memory	Quad Flat Packages	SN74V3640-7PEU	3D model available Symbol and footprint available 3	1 Download Model

	SN74V273-6PZA Texas Instruments	1	FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 80-Pin LQFP Tray	Quad Flat Packages	SN74V273-6PZA	3D model available Symbol and footprint available 3	1 Download Model
	SN74ALVC7805-40DLR Texas Instruments	1	FIFO 256 x 18 3.3-V Synch FIFO Memory	Small Outline Packages	SN74ALVC7805-40DLR	3D model available Symbol and footprint available 3	1 Download Model
	SN74S225N Texas Instruments	1	FIFO Mem Async Dual Width Uni-Dir 16 x 5 20-Pin PDIP Tube	Dual-In-Line Packages	SN74S225N	3D model available Symbol and footprint available 3	1 Download Model
	72V263L7-5BC Renesas Electronics	1	The 72V263 16K x 9/8K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V263L7-5BC	3D model available Symbol and footprint available 3	1 Download Model
	72V295L10PFG Renesas Electronics	1	The 72V295 is an 128K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72V295L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72255LA10TFG8 Renesas Electronics	1	The 72255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72255LA10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72T36135ML6BBI Renesas Electronics	1	The 72T36135M is a 512K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a wide extended x 36 bus to allow ample data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data at very high performance. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36135ML6BBI	3D model available Symbol and footprint available 3	1 Download Model
	72V251L15JGI Renesas Electronics	1	The 72V251 is an 8K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72251 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Plastic Leaded Chip Carrier	72V251L15JGI	3D model not available Symbol and footprint available 2	1 Download Model
	72V3680L7-5BBI Renesas Electronics	1	The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3680L7-5BBI	3D model available Symbol and footprint available 3	1 Download Model
	72V221L15PFG Renesas Electronics	1	The 72V221 is a 1K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72221 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V221L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	72T1845L5BB Renesas Electronics	1	The 72T1845 is a 2K x 18 / 4K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1845L5BB	3D model available Symbol and footprint available 3	1 Download Model

	72V211L15PFGI8 Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V211L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V223L7-5BCI Renesas Electronics	1	The 72V223 1K x 9/512 x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V223L7-5BCI	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L7-5BB8 Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L7-5BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V251L10PFG8 Renesas Electronics	1	The 72V251 is an 8K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72251 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V251L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V36100L7-5PFGI8 Renesas Electronics	1	The 72V36100 64K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V36100L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V2113L7-5BCGI Renesas Electronics	1	The 72V2113 512K x 9/256K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V2113L7-5BCGI	3D model available Symbol and footprint available 3	1 Download Model
	72221L10PFG8 Renesas Electronics	1	The 72221SyncFIFO™ is a 1K x 9 First-In, First-Out memory with clocked read and write controls. This FIFO is useful for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. These FIFOs have 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72221L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72T36125L5BBG Renesas Electronics	1	The 72T36125 is a 256K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36125L5BBG	3D model available Symbol and footprint available 3	1 Download Model
	72T36125L5BBGI Renesas Electronics	1	The 72T36125 is a 256K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36125L5BBGI	3D model available Symbol and footprint available 3	1 Download Model
	72V3640L7-5BB Renesas Electronics	1	The 72V3640 1K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3640L7-5BB	3D model available Symbol and footprint available 3	1 Download Model
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