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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	SN74ACT7811-20FN Texas Instruments	1	IC SYNC FIFO MEM 1024X18 68-PLCC	Plastic Leaded Chip Carrier	SN74ACT7811-20FN	3D model available Symbol and footprint available 3	1 Download Model
	SN74V273-6PZA Texas Instruments	1	FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 18/32K x 9 80-Pin LQFP Tray	Quad Flat Packages	SN74V273-6PZA	3D model available Symbol and footprint available 3	1 Download Model
	SN74V3640-7PEU Texas Instruments	1	FIFO 1024 x 36 Synch FIFO Memory	Quad Flat Packages	SN74V3640-7PEU	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT2229DWR Texas Instruments	1	Synchronous FIFO 512 (256 x 1 x 2) Uni-Directional 60MHz 9ns 28-SOIC	Small Outline Packages	SN74ACT2229DWR	3D model available Symbol and footprint available 3	1 Download Model

	IDT72V05L25JGI Renesas Electronics	1	IDT IDT72V05L25JGI, FIFO Memory, Dual 72kbit, 8K x 9 bit, Bi-Directional 25ns, 3 → 3.6 V, 32-Pin PLCC	Plastic Leaded Chip Carrier	IDT72V05L25JGI	3D model available Symbol and footprint available 3	1 Download Model
	SN74ALVC7805-40DLR Texas Instruments	1	FIFO 256 x 18 3.3-V Synch FIFO Memory	Small Outline Packages	SN74ALVC7805-40DLR	3D model available Symbol and footprint available 3	1 Download Model
	SN74S225N Texas Instruments	1	FIFO Mem Async Dual Width Uni-Dir 16 x 5 20-Pin PDIP Tube	Dual-In-Line Packages	SN74S225N	3D model available Symbol and footprint available 3	1 Download Model
	72V3650L7-5BB8 Renesas Electronics	1	The 72V3650 2K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3650L7-5BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V3690L7-5BBI Renesas Electronics	1	The 72V3690 32K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3690L7-5BBI	3D model available Symbol and footprint available 3	1 Download Model
	72V285L10TFG Renesas Electronics	1	The 72V285 is an 64K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72285 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V285L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72V255LA10TFG8 Renesas Electronics	1	The 72V255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72255 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that nee	Quad Flat Packages	72V255LA10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	7283L15PAGI8 Renesas Electronics	1	The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7283L15PAGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V281L10PFG8 Renesas Electronics	1	The 72V281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72281 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle cou	Quad Flat Packages	72V281L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V02L15JG Renesas Electronics	1	The 72V02 is a 1K x 9 dual-port FIFO that operates at Vcc between 3.0V and 3.6V. The device will load and empty data on a first-in/first-out basis. It uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Plastic Leaded Chip Carrier	72V02L15JG	3D model available Symbol and footprint available 3	1 Download Model
	72V245L15PFGI8 Renesas Electronics	1	The 72V245 is a 4K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72245 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V245L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model

	72V293L6PFG Renesas Electronics	1	The 72V293 128K x 9/64K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	Quad Flat Packages	72V293L6PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V3670L6BB Renesas Electronics	1	The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3670L6BB	3D model available Symbol and footprint available 3	1 Download Model
	72V36110L7-5BB Renesas Electronics	1	The 72V36110 128K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V36110L7-5BB	3D model available Symbol and footprint available 3	1 Download Model
	72V233L6BC Renesas Electronics	1	The 72V233 2K x 9/1K x 18 SuperSync II FIFO memory has flexible x9/x18 Bus-Matching on both read and write ports. The variable clock cycle counting delay associated with the latency period found on previous SuperSync devices has been eliminated. SuperSync II FIFOs are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match buses of unequal sizes.	BGA	72V233L6BC	3D model available Symbol and footprint available 3	1 Download Model
	72V261LA10TFG8 Renesas Electronics	1	The 72V261 is a 16K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72261 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle cou	Quad Flat Packages	72V261LA10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V211L15PFGI8 Renesas Electronics	1	The 72V211 is a 512 x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72211 device. and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V211L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V851L10TFG8 Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72255LA10TFG8 Renesas Electronics	1	The 72255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that need to buffer large amounts of data.	Quad Flat Packages	72255LA10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V275L15TFGI8 Renesas Electronics	1	The 72V275 is a 32K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72275 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that nee	Quad Flat Packages	72V275L15TFGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V221L15PFG Renesas Electronics	1	The 72V221 is a 1K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72221 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V221L15PFG	3D model available Symbol and footprint available 3	1 Download Model
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