7-282 Footprint, Symbol and 3D Model search results

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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	690367282276 Würth Elektronik	1	WR-MM Female SMT Connector with Polarization without Latch, 22 pins, SMT, straight	Other	690367282276	3D model available Symbol and footprint available 3	1 Download Model
	7282L15PAI8 Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L15PAI8	3D model available Symbol and footprint available 3	1 Download Model
	72821L15PF8 Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	C0805H103J5GAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C0805H103J5GAE7282	3D model available Symbol and footprint available 3	1 Download Model

	C0603H102F5GAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C0603H102F5GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	7282L20PA Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L20PA	3D model available Symbol and footprint available 3	1 Download Model
	C1210H104J5GAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C1210H104J5GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	72825LB10PFG8 Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	7447728215 Würth Elektronik	1	Radial Leaded Wire Wound Inductor WE-TI	Other	7447728215	3D model available Symbol and footprint available 3	1 Download Model
	UCC27282QDRQ1 Texas Instruments	1	Gate Drivers Automotive 3-A, 120-V half bridge driver with 5-V UVLO, interlock and enable 8-SOIC -40 to 125	Small Outline Packages	UCC27282QDRQ1	3D model available Symbol and footprint available 3	1 Download Model
	BD7282YFJ-CE2 ROHM Semiconductor	1	High Speed Operational Amplifiers Nano Cap, Automotive Low Noise & Rail-to-Rail Input/Output High Speed CMOS Operational Amplifiers	Small Outline Packages	BD7282YFJ-CE2	3D model available Symbol and footprint available 3	1 Download Model
	ADV7282WBCPZ Analog Devices	1	Video ICs 10-bit SD Diff Video Decoder w/ I2P Out	Quad Flat No-Lead	ADV7282WBCPZ	3D model available Symbol and footprint available 3	1 Download Model
	UCC27282QDQ1 Texas Instruments	1	Gate Drivers Automotive 3-A, 120-V half bridge driver with 5-V UVLO, interlock and enable 8-SOIC -40 to 125	Small Outline Packages	UCC27282QDQ1	3D model available Symbol and footprint available 3	1 Download Model
	72821L25TFI8 Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L25TFI8	3D model available Symbol and footprint available 3	1 Download Model
	TPM27282-DF8R 3Peak Incorporated	1	120-V Supply, 3.5-A Peak, High-frequency HS and LS Gate Driver	Small Outline No-lead	TPM27282-DF8R	3D model available Symbol and footprint available 3	1 Download Model

	C0603H222F5GAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C0603H222F5GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	C0603H101F5GAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C0603H101F5GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	72825LB15PFGI Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	ADV7282AWBCPZ-RL Analog Devices	1	10-Bit, 4× Oversampled SDTV Video Decoder with Differential Inputs	Quad Flat No-Lead	ADV7282AWBCPZ-RL	3D model available Symbol and footprint available 3	1 Download Model
	ADV7282AWBCPZ-M Analog Devices	1	Video ICs 10-bit SD Diff Video Decoder	Quad Flat No-Lead	ADV7282AWBCPZ-M	3D model available Symbol and footprint available 3	1 Download Model
	72821L15PFI8 Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L15PFI8	3D model available Symbol and footprint available 3	1 Download Model
	2118728-2 TE Connectivity	1	Product Type Features: Frame Material Cold Rolled Steel \| Shielding Type Two-Piece \|	Other	2118728-2	3D model available Symbol and footprint available 3	1 Download Model
	AS-7.3728-20-EXT-SMD-TR RALTRON	1	MHz Crystal, 7.3728 MHz, 13.5 x 4.8 mm, ±30 ppm tolerance, ±50 ppm stability, 20 pF, -40~85°C, SMD	Other	AS-7.3728-20-EXT-SMD-TR	3D model available Symbol and footprint available 3	1 Download Model
	72821L15PF Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L15PF	3D model available Symbol and footprint available 3	1 Download Model
	72825LB25PF8 Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB25PF8	3D model available Symbol and footprint available 3	1 Download Model
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