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72851L25TF8
Integrated Device Technology Inc
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1 | TQFP-64, Reel | 72851L25TF8 |
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72851L15PFG
Integrated Device Technology Inc
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1 | FIFO, 8KX9, 10ns, Synchronous, CMOS, PQFP64, GREEN, TQFP-64 | 72851L15PFG |
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72851L10TF
Integrated Device Technology Inc
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1 | TQFP-64, Tray | 72851L10TF |
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72851L15TFG8
Integrated Device Technology Inc
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1 | FIFO, 8KX9, 10ns, Synchronous, CMOS, PQFP64, GREEN, SLIM, TQFP-64 | 72851L15TFG8 |
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72851L25TFGI8
Integrated Device Technology Inc
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1 | FIFO, 8KX9, 15ns, Synchronous, CMOS, PQFP64, GREEN, SLIM, TQFP-64 | 72851L25TFGI8 |
0
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72851L20PFSCDS-W
Integrated Device Technology Inc
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1 | FIFO, 16KX9, 12ns, Synchronous, CMOS, PQFP64 | 72851L20PFSCDS-W |
0
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72851L15PFSCDS-W
Integrated Device Technology Inc
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1 | FIFO, 16KX9, 10ns, Synchronous, CMOS, PQFP64 | 72851L15PFSCDS-W |
0
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72851L25PFISCDS-W
Integrated Device Technology Inc
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1 | FIFO, 16KX9, 15ns, Synchronous, CMOS, PQFP64 | 72851L25PFISCDS-W |
0
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72851L25TFSCDS-W
Integrated Device Technology Inc
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1 | FIFO | 72851L25TFSCDS-W |
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72851L35PFSCDS-W
Integrated Device Technology Inc
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1 | FIFO, 16KX9, 20ns, Synchronous, CMOS, PQFP64 | 72851L35PFSCDS-W |
0
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72851L25TFISCDS-W
Integrated Device Technology Inc
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1 | FIFO | 72851L25TFISCDS-W |
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72851L20TFSCDS-W
Integrated Device Technology Inc
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1 | FIFO | 72851L20TFSCDS-W |
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72851L15TFSCDS-W
Integrated Device Technology Inc
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1 | FIFO | 72851L15TFSCDS-W |
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72851L25PFSCDS-W
Integrated Device Technology Inc
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1 | FIFO, 16KX9, 15ns, Synchronous, CMOS, PQFP64 | 72851L25PFSCDS-W |
0
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72851L15PF8
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L15PF8 |
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72851L25PFI8
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L25PFI8 |
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72851L15PF
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L15PF |
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72851L25PF8
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L25PF8 |
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72851L15PFI8
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L15PFI8 |
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72851L10PF
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L10PF |
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Build or Request | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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72851L25PFI
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L25PFI |
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Build or Request | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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72851L25PF
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L25PF |
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Build or Request | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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72851L15PFI
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L15PFI |
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Build or Request | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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72851L10PF8
Renesas Electronics
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1 | The 72851 is a 8K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72851 architecture lends itself to many flexible configurations s | 72851L10PF8 |
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72851327
Yazaki
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0 | 72851327 |
0
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