7-282 Footprint, Symbol and 3D Model search results

Showing 25 of 55196 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72821L10TF8 Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L10TF8	3D model available Symbol and footprint available 3	1 Download Model
	72821L15TF Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L15TF	3D model available Symbol and footprint available 3	1 Download Model
	C0805H103J3GAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C0805H103J3GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	C1812H103JBGAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C1812H103JBGAE7282	3D model available Symbol and footprint available 3	1 Download Model

	C2220H333JCGAF7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C2220H333JCGAF7282	3D model available Symbol and footprint available 3	1 Download Model
	72821L15TF8 Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L15TF8	3D model available Symbol and footprint available 3	1 Download Model
	72821L10TF Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L10TF	3D model available Symbol and footprint available 3	1 Download Model
	C0805H223J5GAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C0805H223J5GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	C1210H222F2GAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C1210H222F2GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	C0402H102J1GAG7282 Yageo Group	1	SMD Indust C0G HT200C, Ceramic, 1000 pF, 5%, 100 VDC, 250 VDC, 200°C, -55°C, C0G, SMD, MLCC, High Temperature, Ultra-Stable, Low Loss, 0.1 % , 100 GOhms, 1.06 mg, 0402, 1mm, 0.5mm, 0.5mm, 0.3mm, 0.3mm, 368, 78 Weeks, 120	Other	C0402H102J1GAG7282	3D model available Symbol and footprint available 3	1 Download Model
	PUCC27282QDRQ1 Texas Instruments	1	Automotive 3-A, 120-V half bridge driver with 5-V UVLO, interlock and enable	Small Outline Packages	PUCC27282QDRQ1	3D model available Symbol and footprint available 3	1 Download Model
	UCC27282D Texas Instruments	1	Gate Drivers 3-A, 120-V half bridge gate driver with 5-V UVLO, interlock and enable 8-SOIC -40 to 125	Small Outline Packages	UCC27282D	3D model available Symbol and footprint available 3	1 Download Model
	1728284 Phoenix Contact	1	SMKDS 1/ 2-3,81 - Printed circuit board terminal, nominal current: 10 A, rated voltage (III/2): 200 V, nominal cross section: 1 mm², number of potentials: 2, number of rows: 1, number of positions per row: 2, product range: SMKDS 1, pitch: 3.81 mm, connection method: Screw connection with tension sleeve, screw head form: L Slotted, mounting: Wave soldering, conductor/PCB connection direction: 35 °, color: green, Pin layout: Linear pinning, Solder pin [P]: 3.5 mm, number of solder pins per potenti	Other	1728284	3D model available Symbol and footprint available 3	1 Download Model
	768772821 Würth Elektronik	1	WE-TI HV Radial Leaded Wire Wound Inductor Size 8095; L = 820 ÂµH; IR = 0.5 A; Isat = 0.56 A; RDC = 1.92 â„¦	Other	768772821	3D model available Symbol and footprint available 3	1 Download Model
	72825LB15PF Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB15PF	3D model available Symbol and footprint available 3	1 Download Model

	72821L10PFG8 Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72821L10PF Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L10PF	3D model available Symbol and footprint available 3	1 Download Model
	690367282676 Würth Elektronik	1	WR-MM Female SMT Connector with Polarization without Latch, 26 pins, SMT, straight	Other	690367282676	3D model available Symbol and footprint available 3	1 Download Model
	C1812H224J5GAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C1812H224J5GAE7282	3D model available Symbol and footprint available 3	1 Download Model
	72825LB10PF Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB10PF	3D model available Symbol and footprint available 3	1 Download Model
	72821L10PF8 Renesas Electronics	1	The 72821 is a 1K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72221 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72821 architecture lends itself to many flexible configurations s	Quad Flat Packages	72821L10PF8	3D model available Symbol and footprint available 3	1 Download Model
	72825LB25PF Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB25PF	3D model available Symbol and footprint available 3	1 Download Model
	DA9072-82V32 Renesas Electronics	1	The DA9072 is a highly integrated, configurable, low quiescent current power management IC (PMIC) that integrates the most common needs for wearables, home automation and low power battery applications. The PMIC comprises a linear charger with power path management, ultra-low quiescent current (Iq) buck regulator and LDO/load switches, analog battery monitor, watchdog and protection features in an I2C configurable compact WLCSP package.DA9072 has several power saving modes to increase battery life whether t	BGA	DA9072-82V32	3D model available Symbol and footprint available 3	1 Download Model
	72825LB15PFI Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB15PFI	3D model available Symbol and footprint available 3	1 Download Model
	C1812H562JDGAE7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C1812H562JDGAE7282	3D model available Symbol and footprint available 3	1 Download Model
1 2 3 4 5 6 7 8 9

Can't find what you're looking for? Request this part

7-282 Model Download Search Results

Popular MOSFET Drivers