CD401 Model Download Search Results
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CD40110BEE4
Texas Instruments
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1 | Counter/Latch/Decoder/Driver Single 5-Bit Decade UP/Down 16-Pin PDIP Tube | Dual-In-Line Packages | CD40110BEE4 |
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CD4017BM96
Texas Instruments
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1 | TEXAS INSTRUMENTS - CD4017BM96 - COUNTER, DECADE/DIVIDER, 11MHZ, SOIC-16 | Small Outline Packages | CD4017BM96 |
3
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CD4018BEE4
Texas Instruments
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1 | Counter/Divider Single 5-Bit Binary UP 16-Pin PDIP Tube | Dual-In-Line Packages | CD4018BEE4 |
3
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CD40107BEE4
Texas Instruments
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1 | NAND Gate 2-Element 2-IN CMOS 8-Pin PDIP Tube | Dual-In-Line Packages | CD40107BEE4 |
3
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CD40117BE
Texas Instruments
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1 | Programmable Dual 4-Bit Terminator (20V Rating) | Dual-In-Line Packages | CD40117BE |
3
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CD4011BPWR
Texas Instruments
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1 | Texas Instruments CD4011BPWR, Quad 2-Input NAND Logic Gate, 3 → 18 V, 14-Pin TSSOP | Small Outline Packages | CD4011BPWR |
3
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CD4017BF
Texas Instruments
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1 | CMOS Counter/Divider | Ceramic Dual-In-Line Packages | CD4017BF |
3
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CD4015BDMSR
Renesas Electronics
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1 | CD4015BMS consists of two identical, independent, 4-stage serial-input/parallel output registers. Each register has independent CLOCK and RESET inputs as well as a single serial DATA input. Q outputs are available from each of the four stages on both registers. All register stages are D type, master-slave flip-flops. The logic level present at the DATA input is transferred into the first register stage and shifted over one stage at each positive-going clock transition. Resetting of all stages is accomplishe | Dual-In-Line Packages | CD4015BDMSR |
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CD40107BM96G4
Texas Instruments
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1 | IC GATE NAND 2CH 2-INP 8-SOIC | Small Outline Packages | CD40107BM96G4 |
3
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CD40109BPWRG4
Texas Instruments
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1 | Translation - Voltage Levels CMOS Quad Lo-to-Hi Vltg Level Shifter | Small Outline Packages | CD40109BPWRG4 |
3
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CD40161BPW
Texas Instruments
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1 | Counter Shift Registers CMOS Synch Prgrmbl 4B Binary Counter | Small Outline Packages | CD40161BPW |
3
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CD4018BPWE4
Texas Instruments
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1 | Counter ICs CMOS Presettable Divide-By-N Counter | Small Outline Packages | CD4018BPWE4 |
3
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CD40109BPWRE4
Texas Instruments
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1 | Translation - Voltage Levels Quad L-H Voltage | Small Outline Packages | CD40109BPWRE4 |
3
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CD40106BNSR
Texas Instruments
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1 | CMOS Hex Schmitt Triggers | Small Outline Packages | CD40106BNSR |
3
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CD4016BM
Texas Instruments
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1 | TEXAS INSTRUMENTS - CD4016BM . - Analogue Switch, Bilateral Quad, 4 Channels, SPST, 850 ohm, 3V to 18V, SOIC, 14 Pins | Small Outline Packages | CD4016BM |
3
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CD4011BE
Texas Instruments
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1 | CD4011BE, Logic Gate Quad 2 Input NAND, 4.2mA 3 → 18 V 14-Pin PDIP | Dual-In-Line Packages | CD4011BE |
3
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CD4010BEE4
Texas Instruments
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1 | Buffer/Converter 6-CH Non-Inverting CMOS 16-Pin PDIP Tube | Dual-In-Line Packages | CD4010BEE4 |
3
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CD40175BMT
Texas Instruments
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1 | Texas Instruments CD40175BMT, Quad, D Type Flip Flop, 3 → 18 V, 16-Pin SOIC | Small Outline Packages | CD40175BMT |
3
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CD4016BM96E4
Texas Instruments
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1 | IC QUAD BILATERAL SWITCH 14-SOIC | Small Outline Packages | CD4016BM96E4 |
3
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CD4018BE
Texas Instruments
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1 | CMOS PRESETTABLE DIVIDE-BY-N- COUNTERS | Dual-In-Line Packages | CD4018BE |
3
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CD4017BM
Texas Instruments
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1 | 3 V ~ 18 V Counter IC Counter, Decade 1 Element 10 Bit Positive, Negative 16-SOIC | Small Outline Packages | CD4017BM |
3
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CD40107BF3A
Texas Instruments
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1 | NAND Buffer/Driver Gate 2-Element 2-IN CMOS 14-Pin CDIP Tube | Ceramic Dual-In-Line Packages | CD40107BF3A |
3
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CD4011BEE4
Texas Instruments
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1 | NAND Gate 4-Element 2-IN CMOS 14-Pin PDIP Tube | Dual-In-Line Packages | CD4011BEE4 |
3
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Download Model | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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CD4019BEE4
Texas Instruments
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1 | CD4019BEE4, Logic Gate Quad 2 Input AND/OR, 4.2mA 3 → 18 V 16-Pin PDIP | Dual-In-Line Packages | CD4019BEE4 |
3
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Download Model | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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CD40174BM96E4
Texas Instruments
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1 | IC D-TYPE POS TRG SNGL 16SOIC | Small Outline Packages | CD40174BM96E4 |
3
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Download Model | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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