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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72615L35J Renesas Electronics	1	The 72615 is a 512 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Plastic Leaded Chip Carrier	72615L35J	3D model not available Symbol and footprint available 2	1 Download Model
	72T36115L6-7BB Renesas Electronics	1	The 72T36115 is a 128K x 36 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x36/x18/x9 data flow. TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T36115L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72T1875L6-7BB Renesas Electronics	1	The 72T1875 is a 16K x 18 / 32K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1875L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	W631GG8NB11K Winbond This part was updated within the past 30 days. Set alerts for model updates on the part download page.	1	Power Supply: VDD, VDDQ = 1.5V ± 0.075V\r\n Double Data Rate architecture: two data transfers per clock cycle\r\n Eight internal banks for concurrent operation\r\n 8 bit prefetch architecture\r\n CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14\r\n Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)\r\n Programmable read burst ordering: interleaved or nibble sequential\r\n Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received wit	BGA	W631GG8NB11K	3D model available Symbol and footprint available 3	1 Download Model

	CS82C50A-5Z Renesas Electronics	1	The 82C50A Asynchronous Communication Element (ACE) is a high performance programmable Universal Asynchronous Receiver/Transmitter (UART) and Baud Rate Generator (BRG) on a single chip. Using Intersil's advanced Scaled SAJI IV CMOS Process, the ACE will support data rates from DC to 625K baud (0-10MHz clock). The ACE's receiver circuitry converts start, data, stop, and parity bits into a parallel data word. The transmitter circuitry converts a parallel data word into serial form and appends the start, parit	Dual-In-Line Packages	CS82C50A-5Z	3D model available Symbol and footprint available 3	1 Download Model
	7285L20PA Renesas Electronics	1	The 7285 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7285L20PA	3D model available Symbol and footprint available 3	1 Download Model
	72T1855L6-7BB Renesas Electronics	1	The 72T1855 is a 4K x 18 / 8K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T1855L6-7BB	3D model available Symbol and footprint available 3	1 Download Model
	72615L50PF8 Renesas Electronics	1	The 72615 is a 512 x 18 x 2 bidirectional First-In/First-Out memory, with synchronous interface for fast read and write cycle times. The SyncBiFIFO™ is a data buffer that can store or retrieve information from two sources simultaneously. Two Dual-Port FIFO memory arrays are contained in the SyncBiFIFO; one data buffer for each direction. The SyncBiFIFO has registers on all inputs and outputs. Data is only transferred into the I/O registers on clock edges, hence the interfaces are synchronous.	Quad Flat Packages	72615L50PF8	3D model available Symbol and footprint available 3	1 Download Model
	W631GG8NB15A Winbond This part was updated within the past 30 days. Set alerts for model updates on the part download page.	1	Power Supply: VDD, VDDQ = 1.5V ± 0.075V\r\n Double Data Rate architecture: two data transfers per clock cycle\r\n Eight internal banks for concurrent operation\r\n 8 bit prefetch architecture\r\n CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14\r\n Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)\r\n Programmable read burst ordering: interleaved or nibble sequential\r\n Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received wit	BGA	W631GG8NB15A	3D model available Symbol and footprint available 3	1 Download Model
	W631GG6NB15A Winbond This part was updated within the past 30 days. Set alerts for model updates on the part download page.	1	Power Supply: VDD, VDDQ = 1.5V ± 0.075V\r\n⚫ Double Data Rate architecture: two data transfers per clock cycle\r\n⚫ Eight internal banks for concurrent operation\r\n⚫ 8 bit prefetch architecture\r\n⚫ CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14\r\n⚫ Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)\r\n⚫ Programmable read burst ordering: interleaved or nibble sequential\r\n⚫ Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received wit	BGA	W631GG6NB15A	3D model available Symbol and footprint available 3	1 Download Model
	7282L12PA8 Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L12PA8	3D model available Symbol and footprint available 3	1 Download Model
	74ALVCH16260PAG8 Renesas Electronics	1	The 74ALVCH16260 12-bit to 24-bit multiplexed D-type latch is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory interleaving applications. The 74ALVCH16260 has "bus-hold" which prevents floating inputs and eliminates the need for pull-up/down resistors. The 74	Small Outline Packages	74ALVCH16260PAG8	3D model available Symbol and footprint available 3	1 Download Model
	7282L15PA8 Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L15PA8	3D model available Symbol and footprint available 3	1 Download Model
	W631GG8MB12W Winbond This part was updated within the past 30 days. Set alerts for model updates on the part download page.	1	 Power Supply: VDD, VDDQ = 1.5V ± 0.075V\r\n Double Data Rate architecture: two data transfers per clock cycle\r\n Eight internal banks for concurrent operation\r\n 8 bit prefetch architecture\r\n CAS Latency: 5, 6, 7, 8, 9, 10, 11, 13 and 14\r\n Burst length 8 (BL8) and burst chop 4 (BC4) modes: fixed via mode register (MRS) or selectable OnThe-Fly (OTF)\r\n Programmable read burst ordering: interleaved or nibble sequential\r\n Bi-directional, differential data strobes (DQS and DQS#) are transmitted / received w	BGA	W631GG8MB12W	3D model available Symbol and footprint available 3	1 Download Model
	2274215-1 TE Connectivity	1	Mini-SAS HD, Cage, .75in [.03mm] Centerline, Signal, Operating Temperature Range -55 – 85 °C [-67 – 185 °F], Data Rate (Max) 12 Gb/s, 36 Position	Other	2274215-1	3D model available Symbol and footprint available 3	1 Download Model

	72V3624L10PF8 Renesas Electronics	1	The 72V3624 is a 3.3V version of the IDT723624. Two independent 256 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions.	Quad Flat Packages	72V3624L10PF8	3D model available Symbol and footprint available 3	1 Download Model
	401-51703-51 ept	1	data transfer rate 16+ Gbit/s, for PCIe Gen4, for 5 mm board-to-board distance, 40 contacts, termination technology SMT, pitch 0.5 mm, Parallel, SMT, High Density, High Speed	Other	401-51703-51	3D model available Symbol and footprint available 3	1 Download Model
	2392899-1 TE Connectivity	1	QSFP-DD, Connector, .031in [.8mm] Centerline, Signal, Operating Temperature Range -55 – 85 °C [-67 – 185 °F], Data Rate (Max) 112 Gb/s, 152 Position	Other	2392899-1	3D model available Symbol and footprint available 3	1 Download Model
	401-51403-51 ept	1	data transfer rate 16+ Gbit/s, for PCIe Gen4, for 5 mm board-to-board distance, 120 contacts, termination technology SMT, pitch 0.5 mm, Parallel, SMT, High Density, High Speed	Other	401-51403-51	3D model available Symbol and footprint available 3	1 Download Model
	401-55303-51 ept	1	data transfer rate 16+ Gbit/s, for PCIe Gen4, for 8 mm board-to-board distance, 160 contacts, termination technology SMT, pitch 0.5 mm, Parallel, SMT, High Density, High Speed	Other	401-55303-51	3D model available Symbol and footprint available 3	1 Download Model
	1418637 Phoenix Contact	1	Sample set, Ethernet, 8-position, Socket, straight, M12, coding: X - data , PCB mounting, SMD, Alternative product in accordance with RoHS II without Exemption 6c (Pb <0.1%) item no.: 1239202	Other	1418637	3D model available Symbol and footprint available 3	1 Download Model
	LAMBDA62C-9S RF SOLUTIONS	1	FM TRANSCEIVER MODULE, 915MHZ; RF Modulation:FM, FSK, GFSK, GMSK, LoRa, MSK, OOK; Data Rate Max:300Kbps; Frequency Max:915MHz; Sensitivity dBm:-148dBm; Supply Voltage Min:1.8V; Supply Voltage Max:3.7V; Transmit Power:22dBm; Module RoHS Compliant: Yes	Other	LAMBDA62C-9S	3D model available Symbol and footprint available 3	1 Download Model
	AM-RT14-433P RF SOLUTIONS	1	AM TX MODULE, 9.6KBPS, 433.92MHZ; RF Modulation:AM; Data Rate Max:9.6Kbps; Frequency:433.92MHz; Sensitivity dBm:-; Supply Voltage Min:2V; Supply Voltage Max:9V; Supply Current:8mA; RF Transmitter Applications:Security Sys, Car RoHS Compliant: Yes	Other	AM-RT14-433P	3D model available Symbol and footprint available 3	1 Download Model
	ZPT-8RS RF SOLUTIONS	1	RADIO TELEMETRY MODULE, FM, 868MHZ; RF Modulation:FM; Data Rate Max:-; Frequency:868MHz; Sensitivity dBm:-121dBm; Supply Voltage Min:1.8V; Supply Voltage Max:3.6V; Supply Current:-; Supported Devices - RF Receivers:-; RF Receiver RoHS Compliant: Yes	Other	ZPT-8RS	3D model available Symbol and footprint available 3	1 Download Model
	71V67703S80BQI8 Renesas Electronics	1	The 71V67703 3.3V CMOS SRAM is organized as 256K x 36. The 71V67703 SRAM contains write, data, address and control registers. There are no registers in the data output path (flow-through architecture). The burst mode feature offers the highest level of performance to the system designer, as it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V67703S80BQI8	3D model available Symbol and footprint available 3	1 Download Model
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