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Image Part Number D.S Description Package Category Prices / Stock Model Action
Image Part Number D.S Description Package Category Prices / Stock Model Action
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-S-S 1 Download Model
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SLY8SMD03656G Fischer Elektronik GmbH & Co. KG
1 Dual Row, SMD, Male, Pitch 2 x 2mm, 56 Position Other SLY8SMD03656G 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-TM-S 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-G-S 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-FM-S 1 Download Model
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SLVW203656Z Fischer Elektronik GmbH & Co. KG
1 Dual Row, Male, Pitch 1.27 x 2.54 mm; suitable for female header BLM, THT, 56 Position Other SLVW203656Z 1 Download Model
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SLY8SMD03656Z Fischer Elektronik GmbH & Co. KG
1 Dual Row, SMD, Male, Pitch 2 x 2mm, 56 Position Other SLY8SMD03656Z 1 Download Model
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SLVW403656Z Fischer Elektronik GmbH & Co. KG
1 Dual Row, Male, Pitch 1.27 x 1.27 mm, THT, 56 Position Other SLVW403656Z 1 Download Model
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SLVW5SMD03656Z Fischer Elektronik GmbH & Co. KG
1 Dual Row, SMD, Male, Pitch 1.27 x 1.27mm, 56 Position Other SLVW5SMD03656Z 1 Download Model
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SLVW5SMD03656G Fischer Elektronik GmbH & Co. KG
1 Dual Row, SMD, Male, Pitch 1.27 x 1.27mm, 56 Position Other SLVW5SMD03656G 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-F-S 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-T-S 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-H-S 1 Download Model
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SLY8SMD03656S Fischer Elektronik GmbH & Co. KG
1 Dual Row, SMD, Male, Pitch 2 x 2mm, 56 Position Other SLY8SMD03656S 1 Download Model
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SLVW403656G Fischer Elektronik GmbH & Co. KG
1 Dual Row, Male, Pitch 1.27 x 1.27 mm, THT, 56 Position Other SLVW403656G 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-L-S 1 Download Model
Part Image Part Image 1 36 Position, Single-Row .050" x .100" Micro Terminal Strip Other TMS-136-56-SM-S 1 Download Model
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72V3656L10PFI8 Renesas Electronics
1 The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO's can be combined with unidirectional FIFO's capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion. Quad Flat Packages 72V3656L10PFI8 1 Download Model
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SLVW203656G Fischer Elektronik GmbH & Co. KG
1 Dual Row, Male, Pitch 1.27 x 2.54 mm; suitable for female header BLM, THT, 56 Position Other SLVW203656G 1 Download Model
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72V3656L10PFI Renesas Electronics
1 The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO's can be combined with unidirectional FIFO's capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion. Quad Flat Packages 72V3656L10PFI 1 Download Model
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72V3656L15PF Renesas Electronics
1 The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO's can be combined with unidirectional FIFO's capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion. Quad Flat Packages 72V3656L15PF 1 Download Model
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723656L15PF8 Renesas Electronics
1 The 723656 is a 2K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode. Quad Flat Packages 723656L15PF8 1 Download Model
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72V3656L10PF Renesas Electronics
1 The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO's can be combined with unidirectional FIFO's capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion. Quad Flat Packages 72V3656L10PF 1 Download Model
Part Image Part Image
72V3656L10PF8 Renesas Electronics
1 The 72V3656 is a 2K x 36 x 2 Triple Bus sync FIFO memory that is a 3.3V version of the 723656. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. This device can operate in the IDT Standard mode or First Word Fall Through mode. Two 72V3656 FIFO's can be combined with unidirectional FIFO's capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion. Quad Flat Packages 72V3656L10PF8 1 Download Model
Part Image Part Image
723656L15PF Renesas Electronics
1 The 723656 is a 2K x 36 x 2 Triple Bus sync FIFO memory has two independent dual-port SRAM FIFOs on board each chip that can buffer data between a bidirectional 36-bit bus and two unidirectional 18-bit buses. FIFO data can be read and written using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. Communication between each port may bypass the FIFOs via two mailbox registers. This device can operate in the IDT Standard mode or the first word fall through mode. Quad Flat Packages 723656L15PF 1 Download Model
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