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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	71V65703S80PFGI8 Renesas Electronics	1	The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65703S80PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S150BGI Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S150BGI	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S100BQI Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S100BQI	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S133BGI Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S133BGI	3D model available Symbol and footprint available 3	1 Download Model

	71V65803S133BG8 Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S133BG8	3D model available Symbol and footprint available 3	1 Download Model
	71V65703S75BGG8 Renesas Electronics	1	The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65703S75BGG8	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S100BQG8 Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S100BQG8	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S150BQ8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S150BQ8	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S133BQG Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S133BQG	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S133BGI8 Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S133BGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S150BQI8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S150BQI8	3D model available Symbol and footprint available 3	1 Download Model
	71V65903S80BQ8 Renesas Electronics	1	The 71V65903 3.3V CMOS SRAM is organized as 512K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65903 contain address, data-in and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65903S80BQ8	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S150BGGI8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S150BGGI8	3D model available Symbol and footprint available 3	1 Download Model
	71V65703S80BQG Renesas Electronics	1	The 71V65703 3.3V CMOS SRAM is organized as 256K x 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65703 contain address, data-in and control signal registers. The outputs are flow-through (no output data register). In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65703S80BQG	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S100BQGI8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S100BQGI8	3D model available Symbol and footprint available 3	1 Download Model

	71V65803S133BG Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S133BG	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S150BQI Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S150BQI	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S133BQ Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S133BQ	3D model available Symbol and footprint available 3	1 Download Model
	71V65803S100BQG Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S100BQG	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S100PFG Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65603S100PFG	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S100BG8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S100BG8	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S133BQI Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65603S133BQI	3D model available Symbol and footprint available 3	1 Download Model
	71V65903S85PFGI8 Renesas Electronics	1	The 71V65903 3.3V CMOS SRAM is organized as 512K x 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65903 contain address, data-in and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65903S85PFGI8	3D model not available Symbol and footprint available 2	1 Download Model
	71V65803S133BGGI Renesas Electronics	1	The 71V65803 3.3V CMOS SRAM organized as 512K X 18. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65803 contains data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	BGA	71V65803S133BGGI	3D model available Symbol and footprint available 3	1 Download Model
	71V65603S150PFG8 Renesas Electronics	1	The 71V65603 3.3V CMOS SRAM is organized as 256K X 36. It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, it has been given the name ZBTTM, or Zero Bus Turnaround. The 71V65603 contain data I/O, address and control signal registers. In the burst mode, it can provide four cycles of data for a single address presented to the SRAM.	Quad Flat Packages	71V65603S150PFG8	3D model available Symbol and footprint available 3	1 Download Model
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