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7280L20PA
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L20PA |
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7280L20PA8
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L20PA8 |
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7280L12PA
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L12PA |
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7280L12PA8
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L12PA8 |
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7280L12PAG8
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L12PAG8 |
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7280L15PA
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L15PA |
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7280L12PAG
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L12PAG |
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7280L15PA8
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L15PA8 |
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7280L15PAI
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L15PAI |
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7280L15PAI8
Renesas Electronics
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1 | The 7280 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. | Small Outline Packages | 7280L15PAI8 |
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1-967280-1
TE Connectivity
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1 | 5mm R/A automotive PCB header, 42P | Other | 1-967280-1 |
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RC0805FR-07280KL
Yageo Group
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1 | YAGEO (PHYCOMP) RC0805 280K | Resistor Chip | RC0805FR-07280KL |
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RC1206FR-07280RL
Yageo Group
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1 | YAGEO - RC1206FR-07280RL - SMD Chip Resistor, 280 ohm, ± 1%, 250 mW, 1206 [3216 Metric], Thick Film, General Purpose | Resistor Chip | RC1206FR-07280RL |
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RC0201FR-07280RL
Yageo Group
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1 | Thick Film Resistors - SMD | Resistor Chip | RC0201FR-07280RL |
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ADS7280IRSAT
Texas Instruments
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1 | Low-Power, 14-Bit, 1-MHz, Single/Dual Unipolar Input, ADCs with Serial Interface | Quad Flat No-Lead | ADS7280IRSAT |
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T521D476M020ATE0407280
Yageo Group
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1 | Tantalum Capacitors - Polymer SMD 20V 47uF 2917 20% ESR=40mOhms | Capacitor Moulded Polarised | T521D476M020ATE0407280 |
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T495D477K006ZTE1507280
Yageo Group
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1 | Cap Tant Solid 470uF 6.3V D CASE 10% (7.3 X 4.3 X 2.8mm) SMD 7343-31 0.15 Ohm 125C T/R | Other | T495D477K006ZTE1507280 |
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TPS3703A7280DSERQ1
Texas Instruments
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1 | Supervisory Circuits Automotive high-accuracy window supervisor with reset time delay 6-WSON -40 to 125 | Small Outline No-lead | TPS3703A7280DSERQ1 |
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T495A475K020ZTE1K87280
Yageo Group
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1 | Cap Tant Solid 4.7uF 20V A CASE 10% (3.2 X 1.6 X 1.6mm) SMD 3216-18 1.8 Ohm 125C T/R | Capacitor Moulded Polarised | T495A475K020ZTE1K87280 |
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SIT1602BI-13-XXE-7.372800
SiTime
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1 | Low Power, Standard Frequency Oscillator, 2.5x2mm | Other | SIT1602BI-13-XXE-7.372800 |
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T491A105M020AT7280
Yageo Group
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1 | SMD, MnO2, Molded | Other | T491A105M020AT7280 |
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SIT1602BC-11-33N-7.372800
SiTime
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1 | Low Power, Standard Frequency Oscillator, 2.5x2mm | Other | SIT1602BC-11-33N-7.372800 |
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72805LB15PFI
Renesas Electronics
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1 | The 72805 is a 256 x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72205 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for si | Quad Flat Packages | 72805LB15PFI |
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SiT1602BI-72-YYS-7.372800
SiTime
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1 | Low Power, Standard Frequency Oscillator, QFN_2016_4pins | Other | SiT1602BI-72-YYS-7.372800 |
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T498A106M010ATE3K47280
Yageo Group
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1 | T498, Tantalum, MnO2 Tantalum, High Temperature, 10 uF, 20%, 10 VDC, 150°C, -55°C, 85°C, SMD, MnO2, Molded, Hi-Temp, 150C, Auto, AEC-Q200, 4.5 % , N/A, 3.4 Ohms, 1000 nA, 58.6 mg, 3216, 1.6mm, Height Max = 1.8mm, 9000, 156 Weeks | Other | T498A106M010ATE3K47280 |
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