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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72801L10PFG8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72801L10PFG Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72801L15PF Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L15PF	3D model available Symbol and footprint available 3	1 Download Model
	72801L15TFI8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L15TFI8	3D model available Symbol and footprint available 3	1 Download Model

	72801L15PFI8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L15PFI8	3D model available Symbol and footprint available 3	1 Download Model
	72801L10PF Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L10PF	3D model available Symbol and footprint available 3	1 Download Model
	72801L25TF Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L25TF	3D model available Symbol and footprint available 3	1 Download Model
	72801L25TF8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L25TF8	3D model available Symbol and footprint available 3	1 Download Model
	72801L15TF Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L15TF	3D model available Symbol and footprint available 3	1 Download Model
	72801L25PFI8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L25PFI8	3D model available Symbol and footprint available 3	1 Download Model
	72801L25PF8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L25PF8	3D model available Symbol and footprint available 3	1 Download Model
	72801L25TFI Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L25TFI	3D model available Symbol and footprint available 3	1 Download Model
	72801L15TFI Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L15TFI	3D model available Symbol and footprint available 3	1 Download Model
	72801L15PF8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	72801L15TF8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L15TF8	3D model available Symbol and footprint available 3	1 Download Model

	72801L25PFI Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L25PFI	3D model not available Symbol and footprint available 2	1 Download Model
	72801L10PF8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L10PF8	3D model available Symbol and footprint available 3	1 Download Model
	72801L25TFI8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L25TFI8	3D model available Symbol and footprint available 3	1 Download Model
	72801L10TF8 Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L10TF8	3D model available Symbol and footprint available 3	1 Download Model
	72801L15PFI Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L15PFI	3D model available Symbol and footprint available 3	1 Download Model
	72801L10TF Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L10TF	3D model available Symbol and footprint available 3	1 Download Model
	72801L25PF Renesas Electronics	1	The 72801 is a 256 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72201 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72801 architecture lends itself to many flexible configurations	Quad Flat Packages	72801L25PF	3D model available Symbol and footprint available 3	1 Download Model
	831072801 Würth Elektronik	1	WE-SPXO Crystal Oscillator IQXO-791; 2.5 x 2.0mm; 8.0 MHz; Tol = IN; Stab = Â±50 ppm; HCMOS; Temp Range: -40 to 85 Â°C; Vsupply = 3.3 V	Other	831072801	3D model available Symbol and footprint available 3	1 Download Model
	1-967280-1 TE Connectivity	1	5mm R/A automotive PCB header, 42P	Other	1-967280-1	3D model available Symbol and footprint available 3	1 Download Model
	LFSPXO072801 IQD	1	8 MHz XO (Standard) HCMOS Oscillator 3.3V Enable/Disable 4-SMD, No Lead	Other	LFSPXO072801	3D model available Symbol and footprint available 3	1 Download Model
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