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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	7281-8PG-300 Switchcraft	1	Conn Field Installable PIN 8 POS Solder ST Thru-Hole 8 Terminal 1 Port Bulk	Other	7281-8PG-300	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PAI8 Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAI8	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PA Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PA	3D model available Symbol and footprint available 3	1 Download Model
	7281L12PAG8 Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L12PAG8	3D model available Symbol and footprint available 3	1 Download Model

	7281L15PAG Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PAGI Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAGI	3D model available Symbol and footprint available 3	1 Download Model
	7281L12PA8 Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L12PA8	3D model available Symbol and footprint available 3	1 Download Model
	7281L12PA Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L12PA	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PAGI8 Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAGI8	3D model available Symbol and footprint available 3	1 Download Model
	7281L20PA Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L20PA	3D model available Symbol and footprint available 3	1 Download Model
	7281L20PA8 Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L20PA8	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PA8 Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PA8	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PAG8 Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAG8	3D model available Symbol and footprint available 3	1 Download Model
	7281L15PAI Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L15PAI	3D model available Symbol and footprint available 3	1 Download Model
	7281L12PAG Renesas Electronics	1	The 7281 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7281L12PAG	3D model available Symbol and footprint available 3	1 Download Model

	MQ-7.3728-12-30/30/4085 MERCURY	1	Crystal 7.373MHz, ±30ppm, 4-Pin SMD, 7 x 5 x 1.2mm	Other	MQ-7.3728-12-30/30/4085	3D model available Symbol and footprint available 3	1 Download Model
	85728-1008 Molex	1	Modular Connectors / Ethernet Connectors MAGNETICJACK GIGABIT 2X6	Other	85728-1008	3D model available Symbol and footprint available 3	1 Download Model
	PA-SOCKET-SOICW7-28-1.27 Chip Quik	1	Test Sockets Test Socket for SOIC-28W 7.5mm Wide 1.27mm IC,-55°C to +175°C,AC700V,DC500V	Other	PA-SOCKET-SOICW7-28-1.27	3D model available Symbol and footprint available 3	1 Download Model
	7447728102 Würth Elektronik	1	1 mH Unshielded Wirewound Inductor 440 mA 2.15Ohm Max Radial, Vertical Cylinder	Other	7447728102	3D model available Symbol and footprint available 3	1 Download Model
	DA7281-00FVC Renesas Electronics	1	The DA7281 haptic driver with multiple I2C addresses combines custom drive sequences (on- and off-resonance) at up to 1kHz. The DA7281 drives both ERM and LRA (narrow and wideband) actuators and tracks resonance up to 300Hz to provide highly complex click/vibration touch effects in a wide range of applications.The DA7281 combines very low idle current consumption (360nA) with low-latency trigger inputs to minimize the delay after button presses when an application process is in deep sleep.The DA7281 differs	Quad Flat No-Lead	DA7281-00FVC	3D model available Symbol and footprint available 3	1 Download Model
	72815LB10PF8 Renesas Electronics	1	The 72815 is a 512 x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72215 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72815LB10PF8	3D model available Symbol and footprint available 3	1 Download Model
	690367281676 Würth Elektronik	1	WR-MM Female SMT Connector with Polarization without Latch, 16 pins, SMT, straight	Other	690367281676	3D model available Symbol and footprint available 3	1 Download Model
	SIT8008AC-13-33E-7.372810 SiTime	1	Low Power Programmable Oscillator	Other	SIT8008AC-13-33E-7.372810	3D model available Symbol and footprint available 3	1 Download Model
	72811L25TF Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L25TF	3D model available Symbol and footprint available 3	1 Download Model
	72811L15TFI Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L15TFI	3D model available Symbol and footprint available 3	1 Download Model
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