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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72811 Molex	1	Barrier Strip Terminal Block, 25A, 1 Row(s), 1 Deck(s)		72811	3D model not available Symbol and footprint not available 0	0 Build or Request
	72811L10TFG Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72811L10TFG8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72811L10PFG Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L10PFG	3D model available Symbol and footprint available 3	1 Download Model

	72811L10PFG8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72811L25TFI Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L25TFI	3D model available Symbol and footprint available 3	1 Download Model
	72811L15TF8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L15TF8	3D model available Symbol and footprint available 3	1 Download Model
	72811L25PFI8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L25PFI8	3D model available Symbol and footprint available 3	1 Download Model
	72811L15PF Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L15PF	3D model available Symbol and footprint available 3	1 Download Model
	72811L15TFI Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L15TFI	3D model available Symbol and footprint available 3	1 Download Model
	72811L25TF Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L25TF	3D model available Symbol and footprint available 3	1 Download Model
	72811L10TF8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L10TF8	3D model available Symbol and footprint available 3	1 Download Model
	72811L15PFI Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L15PFI	3D model available Symbol and footprint available 3	1 Download Model
	72811L25PFI Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L25PFI	3D model available Symbol and footprint available 3	1 Download Model
	72811L25TF8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L25TF8	3D model available Symbol and footprint available 3	1 Download Model

	72811L25TFI8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L25TFI8	3D model available Symbol and footprint available 3	1 Download Model
	72811L15PF8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	72811L10PF Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L10PF	3D model available Symbol and footprint available 3	1 Download Model
	72811L10PF8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L10PF8	3D model available Symbol and footprint available 3	1 Download Model
	72811L10TF Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L10TF	3D model available Symbol and footprint available 3	1 Download Model
	72811L25PF8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L25PF8	3D model available Symbol and footprint available 3	1 Download Model
	72811L15TF Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L15TF	3D model available Symbol and footprint available 3	1 Download Model
	72811L25PF Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L25PF	3D model available Symbol and footprint available 3	1 Download Model
	72811L15TFI8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L15TFI8	3D model available Symbol and footprint available 3	1 Download Model
	72811L15PFI8 Renesas Electronics	1	The 72811 is a 512 x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72211 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72811 architecture lends itself to many flexible configurations	Quad Flat Packages	72811L15PFI8	3D model available Symbol and footprint available 3	1 Download Model
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