7282- Footprint, Symbol and 3D Model search results

Showing 25 of 55219 results

Price & Stock Powered by

Filter by Manufacturer

Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	7282L15PA Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L15PA	3D model available Symbol and footprint available 3	1 Download Model
	7282L15PA8 Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L15PA8	3D model available Symbol and footprint available 3	1 Download Model
	7282L15PAI Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L15PAI	3D model available Symbol and footprint available 3	1 Download Model
	7282L12PA Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L12PA	3D model available Symbol and footprint available 3	1 Download Model

	7282L12PA8 Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L12PA8	3D model available Symbol and footprint available 3	1 Download Model
	7282L15PAI8 Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L15PAI8	3D model available Symbol and footprint available 3	1 Download Model
	7282L20PA Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L20PA	3D model available Symbol and footprint available 3	1 Download Model
	7282L12PAG8 Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L12PAG8	3D model available Symbol and footprint available 3	1 Download Model
	7282L12PAG Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L12PAG	3D model available Symbol and footprint available 3	1 Download Model
	7282L20PA8 Renesas Electronics	1	The 7282 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7282L20PA8	3D model available Symbol and footprint available 3	1 Download Model
	UCC27282DRCT Texas Instruments	1	120V half-bridge driver with cross conduction protection and low switching losses	Other	UCC27282DRCT	3D model available Symbol and footprint available 3	1 Download Model
	UCC27282QDDAQ1 Texas Instruments	1	AUTOMOTIVE 3-A, 120-V HALF BRIDG	Small Outline Packages	UCC27282QDDAQ1	3D model available Symbol and footprint available 3	1 Download Model
	ADV7282WBCPZ-M-RL Analog Devices	1	Video Decoder 1ADC 10bit Automotive 32-Pin LFCSP EP T/R	Quad Flat No-Lead	ADV7282WBCPZ-M-RL	3D model available Symbol and footprint available 3	1 Download Model
	TCD-17-282X+ Mini-Circuits	1	Signal Conditioning DIR COUP / SURF MT / RoHS	Other	TCD-17-282X+	3D model available Symbol and footprint available 3	1 Download Model
	ADV7282WBCPZ-RL Analog Devices	1	Video Decoder 1ADC 10bit Automotive 32-Pin LFCSP EP T/R	Quad Flat No-Lead	ADV7282WBCPZ-RL	3D model available Symbol and footprint available 3	1 Download Model

	UCC27282DR Texas Instruments	1	Gate Drivers 3-A, 120-V half bridge gate driver with 5-V UVLO, interlock and enable	Small Outline Packages	UCC27282DR	3D model available Symbol and footprint available 3	1 Download Model
	1972820000 Weidmüller	1	PCB connector (board connection), 160 V, 17.5 A, Pitch in mm: 3.81, Number of poles: 10, THT solder connection, Box	Other	1972820000	3D model available Symbol and footprint available 3	1 Download Model
	PF2472-820RF1 Bourns	1	PF2472 820 OHM 1%	Other	PF2472-820RF1	3D model available Symbol and footprint available 3	1 Download Model
	690357282076 Würth Elektronik	1	WR-MM Male SMT Connector 20 pins, SMT, straight	Other	690357282076	3D model available Symbol and footprint available 3	1 Download Model
	DA7282-00FV2 Renesas Electronics	1	The DA7282 ultra-low power haptic driver, combines custom drive sequences, on- and off-resonance, at up to 1kHz. The DA7282 drives both ERM and LRA (narrow and wideband) actuators and track resonance up to 300Hz producing highly complex click/vibration touch effects in a wide range of applications.The DA7282 differs from the DA7280 and DA7281 by providing the capability to go into a full standby mode, lowering current consumption to 5nA.Benefitst20x lower standby current, minimizing the drain on small batte	Quad Flat No-Lead	DA7282-00FV2	3D model available Symbol and footprint available 3	1 Download Model
	690357282676 Würth Elektronik	1	WR-MM Male SMT Connector 26 pins, SMT, straight	Other	690357282676	3D model available Symbol and footprint available 3	1 Download Model
	8-338728-2 TE Connectivity	1	Body Features: Daisy Chain Without \| Primary Product Color Red \| Connector Profile Standard \| Configuration Features: PCB Mount Orientation Vertical \| Number of Rows 2 \| Number of Positions 12 \| Contact Features: Mating Tab Width .028 INCH \| Mating Tab Thickness .016 INCH \| Mating Tab Width .7 MM \| PCB Contact Termination Area Plating Material Thickness 3 â€“ 5 MICM \| Contact Mating Area Plating Material Tin \| Contact Current Rating (Max) 1 AMP \| Contact Base Material Copper Alloy \| Contact Type Pin \| Conta	Other	8-338728-2	3D model available Symbol and footprint available 3	1 Download Model
	72825LB15PF8 Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB15PF8	3D model available Symbol and footprint available 3	1 Download Model
	72825LB10PF8 Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB10PF8	3D model available Symbol and footprint available 3	1 Download Model
	C1206H104J3GAF7282 Yageo Group	1	SMD, MLCC, High Temperature, Ultra-Stable, Low Loss	Other	C1206H104J3GAF7282	3D model available Symbol and footprint available 3	1 Download Model
1 2 3 4 5 6 7 8 9

Can't find what you're looking for? Request this part

7282- Model Download Search Results

Popular FIFOs