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Image Part Number D.S Description Package Category Prices / Stock Model Action
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7283L12PAG8 Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L12PAG8 1 Download Model
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7283L15PAGI8 Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L15PAGI8 1 Download Model
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7283L20PA8 Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L20PA8 1 Download Model
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7283L12PAG Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L12PAG 1 Download Model
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7283L12PA8 Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L12PA8 1 Download Model
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7283L15PAI8 Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L15PAI8 1 Download Model
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7283L15PA Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L15PA 1 Download Model
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7283L15PA8 Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L15PA8 1 Download Model
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7283L15PAI Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L15PAI 1 Download Model
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7283L15PAGI Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L15PAGI 1 Download Model
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7283L20PA Renesas Electronics
1 The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications. Small Outline Packages 7283L20PA 1 Download Model
Part Image Part Image 1 2,1/6,3mm, PCB type 90°, angled contacts, closed circuit, with screen shield Other 072837 1 Download Model
Part Image Part Image 1 CLIK-MATE1.5 DRVT SMT AU0.38 ETP 28P NAT Other 213227-2830 1 Download Model
Part Image Part Image 1 Inductor Power Shielded/Molded Wirewound 33uH 20% 1KHz Ferrite 3A 0.0648Ohm DCR T/R Other PISA4728-330M-04 1 Download Model
Part Image Part Image 1 FFC & FPC Connectors 0.5 FPC ZIF RA 28Ct Sn-Ag-Bi// Other 52437-2833 1 Download Model
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TPS728330185DRVT Texas Instruments
1 Texas Instruments TPS728330185DRVT, LDO Voltage Regulator, 200mA Adjustable, 0.9 → 3.6 V, 3% 6-Pin, SON Small Outline No-lead TPS728330185DRVT 1 Download Model
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TPS728330185DRVR Texas Instruments
1 Single-output LDO, 200 mA, dual-level fixed with Vset pin Small Outline No-lead TPS728330185DRVR 1 Download Model
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717-2834 RS Pro
1 RS Pro RS Series Thick Film Surface Mount Resistor 0805 Case 14kΩ ±1% 0.125W ±100ppm/°C Resistor Chip 717-2834 1 Download Model
Part Image Part Image 1 HIGH RELIABILITY COTS DC-DC CONVERTERS INPUT 28 VOLTS OUTPUT 3.3 V Other VXR7-283R3S 1 Download Model
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1728374 Phoenix Contact
1 MCV 1,5/ 3-G-3,81 P14 THR R32 - PCB headers, nominal cross section: 1.5 mm2, color: black, nominal current: 8 A, rated voltage (III/2): 160 V, contact surface: Sn, contact connection type: Pin, number of potentials: 3, number of rows: 1, number of positions: 3, number of connections: 3, product range: MCV 1,5/..-G-THR, pitch: 3.81 mm, mounting: THR soldering / wave soldering, pin layout: Linear pinning, solder pin [P]: 1.4 mm, number of solder pins per potential: 1, plug-in system: COMBICON MC 1, Other 1728374 1 Download Model
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72831L15TF Renesas Electronics
1 The 72831 is a 2K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations s Quad Flat Packages 72831L15TF 1 Download Model
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72831L10PFG8 Renesas Electronics
1 The 72831 is a 2K x 9 dual synchronous (clocked) FIFO. The device is functionally equivalent to two 72231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each of the two FIFOs has a 9-bit input data port and a 9-bit output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation. The 72831 architecture lends itself to many flexible configurations s Quad Flat Packages 72831L10PFG8 1 Download Model
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1728340000 Weidmüller
1 PCB connector (board connection), 125 V, 10 A, Pitch in mm: 3.50, Number of poles: 12, THT solder connection, Box Other 1728340000 1 Download Model
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1728323 Phoenix Contact
1 SMKDS 1/ 6-3,81 - Printed circuit board terminal, nominal current: 10 A, rated voltage (III/2): 200 V, nominal cross section: 1 mm2, number of potentials: 6, number of rows: 1, number of positions per row: 6, product range: SMKDS 1, pitch: 3.81 mm, connection method: Screw connection with tension sleeve, screw head form: L Slotted, mounting: Wave soldering, conductor/PCB connection direction: 35 °, color: green, Pin layout: Linear pinning, Solder pin [P]: 3.5 mm, number of solder pins per potenti Other 1728323 1 Download Model
Part Image Part Image 1 1.50mm Pitch CLIK-Mate Wire-to-Board PCB Receptacle, Dual Row, Surface Mount, Vertical, 0.38µm Gold (Au) Plating, 28 Circuits, Black Other 2132272831 1 Download Model
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