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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	72V83L20PAGI Renesas Electronics	1	The 72V83 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V83L20PAGI	3D model available Symbol and footprint available 3	1 Download Model
	72V83L20PAGI8 Renesas Electronics	1	The 72V83 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V83L20PAGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V83L15PAG Renesas Electronics	1	The 72V83 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V83L15PAG	3D model available Symbol and footprint available 3	1 Download Model
	72V83L15PAG8 Renesas Electronics	1	The 72V83 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V83L15PAG8	3D model available Symbol and footprint available 3	1 Download Model

	72V831L10PFG8 Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V831L10TFG Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72V831L10PFG Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V831L10TFG8 Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V83L15PA8 Renesas Electronics	1	The 72V83 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V83L15PA8	3D model available Symbol and footprint available 3	1 Download Model
	72V83L20PA8 Renesas Electronics	1	The 72V83 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V83L20PA8	3D model available Symbol and footprint available 3	1 Download Model
	72V83L15PA Renesas Electronics	1	The 72V83 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	72V83L15PA	3D model available Symbol and footprint available 3	1 Download Model
	72V835L15PF8 Renesas Electronics	1	The 72V835 is a 2K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V235 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V835L15PF8	3D model available Symbol and footprint available 3	1 Download Model
	72V835L15PFI8 Renesas Electronics	1	The 72V835 is a 2K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V235 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V835L15PFI8	3D model available Symbol and footprint available 3	1 Download Model
	72V831L10TF Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L10TF	3D model available Symbol and footprint available 3	1 Download Model
	72V831L15TFI8 Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L15TFI8	3D model available Symbol and footprint available 3	1 Download Model

	72V831L20TF Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L20TF	3D model available Symbol and footprint available 3	1 Download Model
	72V835L20PF Renesas Electronics	1	The 72V835 is a 2K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V235 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V835L20PF	3D model available Symbol and footprint available 3	1 Download Model
	72V831L15TF8 Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L15TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V835L20PF8 Renesas Electronics	1	The 72V835 is a 2K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V235 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V835L20PF8	3D model available Symbol and footprint available 3	1 Download Model
	72V831L10TF8 Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L10TF8	3D model available Symbol and footprint available 3	1 Download Model
	72V831L15TFI Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L15TFI	3D model available Symbol and footprint available 3	1 Download Model
	72V835L15PF Renesas Electronics	1	The 72V835 is a 2K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V235 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V835L15PF	3D model available Symbol and footprint available 3	1 Download Model
	72V835L10PF8 Renesas Electronics	1	The 72V835 is a 2K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V235 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V835L10PF8	3D model available Symbol and footprint available 3	1 Download Model
	72V831L15TF Renesas Electronics	1	The 72V831is a 2K x 9 dual synchronous FIFO that is functionally equivalent to two 72V231 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V831L15TF	3D model available Symbol and footprint available 3	1 Download Model
	72V835L15PFI Renesas Electronics	1	The 72V835 is a 2K x 18 dual sync FIFO with clocked read and write controls that is functionally equivalent to two 72V235 FIFO's in a single package with all associated control, data, and flag lines assigned to independent pins. This FIFO is useful for optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous	Quad Flat Packages	72V835L15PFI	3D model available Symbol and footprint available 3	1 Download Model
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