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9DB106BGILF
Renesas Electronics
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1 | The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications. | Small Outline Packages | Check Price & Stock |
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9DB106BGILF
Integrated Device Technology Inc
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1 | TSSOP-28, Tube | Check Price & Stock |
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9DB106BGILFT
Renesas Electronics
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1 | The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a selectable PLL bandwidth to maximize performance in systems with or without Spread-Spectrum clocking. An SMBus interface allows control of the PLL bandwidth and bypass options, while 2 clock request (CLKREQ#) pins make the 9DB106 suitable for Express Card applications. | Small Outline Packages | Check Price & Stock |
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Download Model | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
9DB106BGILFT
Integrated Device Technology Inc
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1 | TSSOP-28, Reel | Check Price & Stock |
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ICS9DB106BGILF
Renesas Electronics
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0 | ICS9DB106BGILF, PLL Clock Buffer, 100 → 100 MHz, 28-Pin TSSOP | Check Price & Stock |
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Build or Request |