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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	LB-10 RLC Electronics Inc	1	Low Pass Filter,		LB-10	3D model not available Symbol and footprint not available 0	0 Build or Request
	EFM8LB10F16E-B-QFN24 Silicon Labs	1	SILICON LABS - EFM8LB10F16E-B-QFN24 - 8 Bit MCU, EFM8 Family EFM8LB Series Microcontrollers, 72 MHz, 16 KB, 1.25 KB, 24 Pins, QFN	Other	EFM8LB10F16E-B-QFN24	3D model available Symbol and footprint available 3	1 Download Model
	EFM8LB10F16E-B-QFN32 Silicon Labs	1	8-bit Microcontrollers - MCU 16kB FLSH/1.25kB RAM 12bADC, +/-3oC	Quad Flat No-Lead	EFM8LB10F16E-B-QFN32	3D model available Symbol and footprint available 3	1 Download Model
	72245LB10JG8 Renesas Electronics	1	The 72245 is a 4K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Plastic Leaded Chip Carrier	72245LB10JG8	3D model available Symbol and footprint available 3	1 Download Model

	72805LB10PF Renesas Electronics	1	The 72805 is a 256 x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72205 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for si	Quad Flat Packages	72805LB10PF	3D model available Symbol and footprint available 3	1 Download Model
	72225LB10TFG Renesas Electronics	1	The 72225 is a 1K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72225LB10TFG	3D model available Symbol and footprint available 3	1 Download Model
	72815LB10PF Renesas Electronics	1	The 72815 is a 512 x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72215 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72815LB10PF	3D model available Symbol and footprint available 3	1 Download Model
	72215LB10PFG8 Renesas Electronics	1	The 72215 is a 512 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain techniqu	Quad Flat Packages	72215LB10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72245LB10TF Renesas Electronics	1	The 72245 is a 4K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72245LB10TF	3D model available Symbol and footprint available 3	1 Download Model
	72825LB10PF8 Renesas Electronics	1	The 72825 is a 1K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72225 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72825LB10PF8	3D model available Symbol and footprint available 3	1 Download Model
	SI5334L-B10720-GM Silicon Labs	1	PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR	Quad Flat No-Lead	SI5334L-B10720-GM	3D model available Symbol and footprint available 3	1 Download Model
	72845LB10PF8 Renesas Electronics	1	The 72845 is a 4K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72845LB10PF8	3D model available Symbol and footprint available 3	1 Download Model
	ELB-1001SYGWA/S530-E2 Everlight	1	LED Circuit Board Indicator LED Circuit Board Indicator Bar - 10 Wide, DIP Green (x 10) Diffused, White 2V 25mA Rectangle with Flat Top 5.00mm x 1.70mm Through Hole	Dual-In-Line Sockets	ELB-1001SYGWA/S530-E2	3D model not available Symbol and footprint available 2	1 Download Model
	RV141F-40E3-18BL-B100K-004 Alpha (Taiwan)	1	Potentiometers Linear 18mm 100K PC MOUNT	Other	RV141F-40E3-18BL-B100K-004	3D model available Symbol and footprint available 3	1 Download Model
	RNLB10G0103B0E ROYALOHM	1	Resistor network: Y; THT; 10kΩ; ±2%; 0.2W; No.of resistors: 5; 100V	Other	RNLB10G0103B0E	3D model available Symbol and footprint available 3	1 Download Model

	72235LB10TFG8 Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72235LB10PFG Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB10PFG	3D model available Symbol and footprint available 3	1 Download Model
	72815LB10PF8 Renesas Electronics	1	The 72815 is a 512 x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72215 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72815LB10PF8	3D model available Symbol and footprint available 3	1 Download Model
	VLB10050HT-R30N TDK	1	SMD / SMT Inductors (Coils), L=300nH, L x W x T :	Other	VLB10050HT-R30N	3D model available Symbol and footprint available 3	1 Download Model
	72205LB10J8 Renesas Electronics	1	The 72205 is a 256 x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain techniqu	Plastic Leaded Chip Carrier	72205LB10J8	3D model not available Symbol and footprint available 2	1 Download Model
	72235LB10PF Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB10PF	3D model available Symbol and footprint available 3	1 Download Model
	VLB10050HT-R12M TDK	1	SMD / SMT Inductors (Coils), L=120nH, L x W x T :	Other	VLB10050HT-R12M	3D model available Symbol and footprint available 3	1 Download Model
	72845LB10PF Renesas Electronics	1	The 72845 is a 4K x 18 First-In, First-Out memory with clocked read and write controls. It is functionally equivalent to two 72245 FIFOs in a single package with all associated control, data, and flag lines assigned to independent pins and would be applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. Each of the two FIFOs has an 18-bit input and output port. The Read Clock can be tied to the Write Clock for	Quad Flat Packages	72845LB10PF	3D model available Symbol and footprint available 3	1 Download Model
	72225LB10PFG8 Renesas Electronics	1	The 72225 is a 1K x 8 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72225LB10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	SI5334L-B10748-GM Silicon Labs	1	PIN-CONTROLLED ANY-FREQUENCY, ANY-OUTPUT QUAD CLOCK GENERATOR	Quad Flat No-Lead	SI5334L-B10748-GM	3D model available Symbol and footprint available 3	1 Download Model
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