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AT25SF321B-SSHB-T - Renesas Electronics

Description: The AT25SF321B is a member of our standard class code and data storage solutions designed for 3V systems in which program code is shadowed from Flash memory into embedded or external RAM for execution.The architecture includes erase block sizes that are optimized to meet the needs of today's code and data storage applications and three security register pages for unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc. Universally compatible pinout and comma

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AT25SF321B-SSHB-T - Renesas Electronics PCB footprint - Small Outline Packages - Small Outline Packages - NOR Flash 32 Mbit, 3.0V (2.7V to 3.6V), -40C to 85C, SOIC-N 150mil (Tape & Reel), Single, Dual, Quad SPI
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3D Models
AT25SF321B-SSHB-T - Renesas Electronics  - 3D model - Small Outline Packages - NOR Flash 32 Mbit, 3.0V (2.7V to 3.6V), -40C to 85C, SOIC-N 150mil (Tape & Reel), Single, Dual, Quad SPI
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AT25SF321B-SSHB-T Details

  • Manufacturer Part Number:

    AT25SF321B-SSHB-T

  • Brand Name:

    Renesas

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    SOIC-N

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.32.00.51

  • Factory Lead Time:

    18 Weeks

  • Manufacturer:

    Renesas Electronics Corporation

  • YTEOL:

    5.5

  • Clock Frequency-Max (fCLK):

    133 MHz

  • Data Retention Time-Min:

    20

  • Endurance:

    100000 Write/Erase Cycles

  • JESD-30 Code:

    R-PDSO-G8

  • JESD-609 Code:

    e4

  • Length:

    4.83 mm

  • Memory Density:

    33554432 bit

  • Memory IC Type:

    FLASH

  • Memory Width:

    8

  • Moisture Sensitivity Level:

    1

  • Number of Functions:

    1

  • Number of Terminals:

    8

  • Number of Words:

    4194304 words

  • Number of Words Code:

    4000000

  • Operating Mode:

    SYNCHRONOUS

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    4MX8

  • Output Characteristics:

    3-STATE

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SOP

  • Package Equivalence Code:

    SOP8,.25

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Parallel/Serial:

    SERIAL

  • Peak Reflow Temperature (Cel):

    260

  • Programming Voltage:

    3 V

  • Seated Height-Max:

    1.75 mm

  • Serial Bus Type:

    QSPI

  • Standby Current-Max:

    0.000005 A

  • Supply Current-Max:

    0.012 mA

  • Supply Voltage-Max (Vsup):

    3.6 V

  • Supply Voltage-Min (Vsup):

    2.7 V

  • Supply Voltage-Nom (Vsup):

    3 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    NICKEL PALLADIUM GOLD

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    1.27 mm

  • Terminal Position:

    DUAL

  • Type:

    NOR TYPE

  • Width:

    3.9 mm

  • Write Protection:

    HARDWARE/SOFTWARE

AT25SF321B-SSHB-T Frequently Asked Questions (FAQs)

  • The AT25SF321B-SSHB-T has a minimum of 100,000 erase cycles, but the actual number of cycles may vary depending on the usage and operating conditions.
  • The hold pin (HOLD#) should be pulled high during power-up and power-down sequences to prevent any unwanted writes or erases. It's recommended to use an external pull-up resistor to ensure the pin is held high.
  • The recommended clock frequency for the AT25SF321B-SSHB-T is up to 50 MHz, but it can operate at frequencies up to 100 MHz with some limitations. Consult the datasheet for specific timing requirements.
  • To securely erase the AT25SF321B-SSHB-T, use the Chip Erase command (0xC7) followed by a series of block erase commands (0x50) to erase all blocks. Then, use the Write Enable command (0x06) to enable writes and write random data to the entire device.
  • The WP# (Write Protect) pin is used to prevent writes to the status register. When WP# is low, the status register is write-protected. When WP# is high, the status register can be written. Use the WP# pin to protect the device from accidental writes or changes to the status register.

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