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XC2C64A-5VQ44C - AMD

Description: IC CPLD 64MC 4.6NS 44VQFP

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XC2C64A-5VQ44C - AMD PCB footprint - Quad Flat Packages - Quad Flat Packages - XC2C64A-5VQ44C
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XC2C64A-5VQ44C - AMD  - 3D model - Quad Flat Packages - XC2C64A-5VQ44C
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XC2C64A-5VQ44C Details

  • Manufacturer Part Number:

    XC2C64A-5VQ44C

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    10 X 10 MM, 0.80 MM PITCH, VQFP-44

  • Country Of Origin:

    Taiwan

  • HTS Code:

    8542.31.00.55

  • Factory Lead Time:

    111 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    0

  • Additional Feature:

    REAL DIGITAL DESIGN TECHNOLOGY

  • Clock Frequency-Max:

    333 MHz

  • In-System Programmable:

    YES

  • JESD-30 Code:

    S-PQFP-G44

  • JESD-609 Code:

    e4

  • JTAG BST:

    YES

  • Length:

    10 mm

  • Moisture Sensitivity Level:

    3

  • Number of I/O Lines:

    33

  • Number of Inputs:

    33

  • Number of Macro Cells:

    64

  • Number of Outputs:

    33

  • Number of Terminals:

    44

  • Operating Temperature-Max:

    70 °C

  • Organization:

    0 DEDICATED INPUTS, 33 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TQFP

  • Package Equivalence Code:

    TQFP44,.47SQ,32

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK, THIN PROFILE

  • Programmable Logic Type:

    FLASH PLD

  • Propagation Delay:

    5 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.2 mm

  • Supply Voltage-Max:

    1.9 V

  • Supply Voltage-Min:

    1.7 V

  • Supply Voltage-Nom:

    1.8 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    COMMERCIAL

  • Terminal Finish:

    NICKEL PALLADIUM GOLD

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.8 mm

  • Terminal Position:

    QUAD

  • Width:

    10 mm

XC2C64A-5VQ44C Frequently Asked Questions (FAQs)

  • The maximum operating frequency of XC2C64A-5VQ44C is 160 MHz.
  • To implement a CDC in XC2C64A-5VQ44C, you can use a synchronizer circuit or a FIFO-based CDC. The synchronizer circuit uses two flip-flops to synchronize the data, while the FIFO-based CDC uses a FIFO to buffer the data and a clock domain crossing circuit to synchronize the read and write clocks.
  • The power consumption of XC2C64A-5VQ44C depends on the operating frequency, voltage, and usage. According to the datasheet, the typical power consumption is around 150 mW at 1.8V and 50 MHz. However, this value can vary depending on the specific application and usage.
  • The I/O banks in XC2C64A-5VQ44C can be configured using the ISE Design Suite software. You can specify the I/O standard, voltage, and slew rate for each bank using the software. Additionally, you can also use the FPGA editor to manually configure the I/O banks.
  • The maximum current that XC2C64A-5VQ44C can source or sink depends on the I/O standard and voltage. According to the datasheet, the maximum current is around 24 mA for 3.3V I/Os and 12 mA for 1.8V I/Os.

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XC2C64A-5VQ44C Overview

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