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XC5VSX35T-1FF665I - AMD

Description: FPGA - Field Programmable Gate Array XC5VSX35T-1FF665I

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PCB Footprints
XC5VSX35T-1FF665I - AMD PCB footprint - BGA - BGA - 665 Ball Flip-Chip BGA Package (FFG665, FF665, FFV665, EF665)
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3D Models
XC5VSX35T-1FF665I - AMD  - 3D model - BGA - 665 Ball Flip-Chip BGA Package (FFG665, FF665, FFV665, EF665)
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XC5VSX35T-1FF665I Details

  • Manufacturer Part Number:

    XC5VSX35T-1FF665I

  • Part Life Cycle Code:

    Active

  • Package Description:

    BGA-665

  • HTS Code:

    8542.31.00.60

  • Factory Lead Time:

    12 Weeks

  • Manufacturer:

    AMD

  • YTEOL:

    6

  • Combinatorial Delay of a CLB-Max:

    0.9 ns

  • JESD-30 Code:

    S-PBGA-B665

  • JESD-609 Code:

    e0

  • Length:

    27 mm

  • Moisture Sensitivity Level:

    4

  • Number of CLBs:

    2720

  • Number of Inputs:

    360

  • Number of Logic Cells:

    34816

  • Number of Outputs:

    360

  • Number of Terminals:

    665

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    2720 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA665,26X26,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Peak Reflow Temperature (Cel):

    225

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.9 mm

  • Supply Voltage-Max:

    1.05 V

  • Supply Voltage-Min:

    0.95 V

  • Supply Voltage-Nom:

    1 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 65 nm

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Lead (Sn63Pb37)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    27 mm

XC5VSX35T-1FF665I Frequently Asked Questions (FAQs)

  • The maximum operating frequency of the XC5VSX35T-1FF665I FPGA is 550 MHz.
  • You can use the Memory Interface Generator (MIG) tool in Vivado Design Suite to generate a DDR3 memory interface. The tool provides a wizard-based interface to configure the memory interface and generates the necessary IP cores.
  • The power consumption of the XC5VSX35T-1FF665I FPGA depends on the specific design and operating conditions. However, Xilinx provides power estimation tools such as XPower Estimator and Power Analyzer to estimate the power consumption of your design.
  • Yes, the XC5VSX35T-1FF665I FPGA is suitable for high-reliability applications. It is fabricated using a 65nm process and has built-in features such as error correction and detection, and is also available in a -Q grade for high-reliability applications.
  • Xilinx provides a range of security features, including bitstream encryption, secure boot, and IP protection. You can use these features to secure your design and prevent unauthorized access or reverse engineering.

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XC5VSX35T-1FF665I Overview

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Image Part Number Model
Part Image XC5VSX35T-1FFG665I AMD

Field Programmable Gate Array, 2720 CLBs, 34816-Cell, CMOS, PBGA665

Part Image XC5VSX35T-1FFG665C AMD

Field Programmable Gate Array, 2720 CLBs, 34816-Cell, CMOS, PBGA665

Part Image XC5VSX35T-1FFV665I AMD

Field Programmable Gate Array, 2720 CLBs, 34816-Cell, CMOS, PBGA665

Part Image XC5VSX35T-1FF665I AMD Xilinx

Field Programmable Gate Array, 2720 CLBs, 34816-Cell, CMOS, PBGA665

Part Image XC5VSX35T-1FFV665I AMD Xilinx

Field Programmable Gate Array, 2720 CLBs, 34816-Cell, CMOS, PBGA665

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