Part Image

SN74SSQEA32882ZALR - Texas Instruments

Description: JEDEC SSTE32882 Compliant 28-Bit to 56-Bit Registered Buffer with Address-Parity Test

Download SN74SSQEA32882ZALR Model
Schematic
symbols
Schematic symbol is unavailable for download
PCB
footprints
PCB footprint is unavailable for download
3D
models
3D model is unavailable for download
Layers
    Zoom
    Zoom Full
    Middle click on footprint to measure