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10AS066H3F34I2SG - Intel

Description: FPGA - Field Programmable Gate Array

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PCB Footprints
10AS066H3F34I2SG - Intel PCB footprint - BGA - BGA - 1152-Pin FineLine Ball-Grid Array (FBGA) - Flip Chip - Flat Top Single-Piece Lid - A:3.35
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3D Models
10AS066H3F34I2SG - Intel  - 3D model - BGA - 1152-Pin FineLine Ball-Grid Array (FBGA) - Flip Chip - Flat Top Single-Piece Lid - A:3.35
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10AS066H3F34I2SG Details

  • Manufacturer Part Number:

    10AS066H3F34I2SG

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Package Description:

    FBGA-1152

  • Country Of Origin:

    Mainland China, Malaysia, Taiwan, USA, Vietnam

  • ECCN Code:

    3A991

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    10

  • JESD-30 Code:

    S-PBGA-B1152

  • Length:

    35 mm

  • Number of CLBs:

    25168

  • Number of Inputs:

    384

  • Number of Logic Cells:

    660000

  • Number of Outputs:

    384

  • Number of Terminals:

    1152

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    25168 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA1152,34X34,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FPGA SOC

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    0.93 V

  • Supply Voltage-Min:

    0.87 V

  • Supply Voltage-Nom:

    0.9 V

  • Surface Mount:

    YES

  • Technology:

    20 nm

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.8 mm

  • Terminal Position:

    BOTTOM

  • Width:

    35 mm

10AS066H3F34I2SG Frequently Asked Questions (FAQs)

  • The 10AS066H3F34I2SG FPGA has an operating temperature range of 0°C to 100°C (commercial temperature range) and -40°C to 100°C (industrial temperature range).
  • Intel recommends using an external POR circuit with a voltage supervisor IC, such as the MAX809, to ensure a reliable power-on reset. The FPGA's internal POR circuit can also be used, but it may not be as reliable.
  • Intel provides guidelines for PCB layout and routing in the '10AS066H3F34I2SG FPGA PCB Design Guidelines' document. It recommends using a 4-layer PCB with a dedicated power plane, and following specific routing rules for high-speed signals.
  • To optimize timing closure, use the Intel Quartus Prime software to analyze and optimize the design. Apply timing constraints, use the 'TimeQuest' timing analyzer, and optimize the design using the 'Optimize For Area' and 'Optimize For Speed' options.
  • The internal voltage regulators should be set to the recommended values: VCCINT = 1.2V, VCCAUX = 2.5V, and VCCIO = 1.8V or 2.5V (depending on the I/O standard used).

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10AS066H3F34I2SG Overview

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