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10M02DCV36C8G - Intel

Description: FPGA - Field Programmable Gate Array non-volatile FPGA, 27 I/O, 36WLCSP

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10M02DCV36C8G - Intel - PCB symbol
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PCB Footprints
10M02DCV36C8G - Intel PCB footprint - Other - Other - 36-Pin Very FineLine Ball-Grid Array (VBGA) – Wafer Level Chip Scale Package (WLCSP) - A:0.54_FF
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3D Models
10M02DCV36C8G - Intel - 3D model - Other - 36-Pin Very FineLine Ball-Grid Array (VBGA) – Wafer Level Chip Scale Package (WLCSP) - A:0.54_FF
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10M02DCV36C8G Details

  • Manufacturer Part Number:

    10M02DCV36C8G

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Package Description:

    WLCSP-36

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    8

  • JESD-30 Code:

    R-PBGA-B36

  • Length:

    3.466 mm

  • Moisture Sensitivity Level:

    1

  • Number of CLBs:

    125

  • Number of Inputs:

    246

  • Number of Logic Cells:

    2000

  • Number of Outputs:

    246

  • Number of Terminals:

    36

  • Operating Temperature-Max:

    85 °C

  • Organization:

    125 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA36,6X6,16

  • Package Shape:

    RECTANGULAR

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    0.54 mm

  • Supply Voltage-Max:

    1.25 V

  • Supply Voltage-Min:

    1.15 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    55 nm

  • Temperature Grade:

    COMMERCIAL EXTENDED

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    BOTTOM

  • Width:

    3.396 mm

10M02DCV36C8G Frequently Asked Questions (FAQs)

  • Intel recommends a 4-layer PCB with a solid ground plane and thermal vias to dissipate heat efficiently. A minimum of 2 oz copper thickness is recommended for optimal thermal performance.
  • Intel recommends a power-up sequence of VCCIO, then VCC, and finally VREF. A power-down sequence of VREF, then VCC, and finally VCCIO is recommended. A minimum of 10 ms delay is recommended between power-up and power-down sequences.
  • The maximum operating temperature for the 10M02DCV36C8G is 100°C (TJ). However, Intel recommends operating the device at a maximum temperature of 85°C (TJ) for optimal reliability and performance.
  • Intel recommends using a CDC synchronizer or a FIFO-based CDC solution to handle clock domain crossing in the 10M02DCV36C8G. The CDC synchronizer should be designed to handle metastability and ensure data integrity.
  • Intel recommends a JTAG configuration with a TCK frequency of 10 MHz or less, and a TMS and TDI signal frequency of 100 kHz or less. The JTAG interface should be designed to handle signal integrity and electromagnetic interference (EMI) issues.

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10M02DCV36C8G Overview

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