Description:The 72V3640 1K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.
RETRANSMIT; AUTO POWER DOWN; ASYNCHRONOUS MODE IS ALSO POSSIBLE
Clock Frequency-Max (fCLK):
100 MHz
Cycle Time:
6 ns
JESD-30 Code:
S-PBGA-B144
JESD-609 Code:
e0
Length:
13 mm
Memory Density:
36864 bit
Memory IC Type:
OTHER FIFO
Memory Width:
36
Moisture Sensitivity Level:
3
Number of Functions:
1
Number of Terminals:
144
Number of Words:
1024 words
Number of Words Code:
1000
Operating Mode:
SYNCHRONOUS
Operating Temperature-Max:
70 °C
Organization:
1KX36
Output Enable:
YES
Package Body Material:
PLASTIC/EPOXY
Package Code:
BGA
Package Equivalence Code:
BGA144,12X12,40
Package Shape:
SQUARE
Package Style:
GRID ARRAY
Parallel/Serial:
PARALLEL
Peak Reflow Temperature (Cel):
225
Qualification Status:
Not Qualified
Seated Height-Max:
1.97 mm
Standby Current-Max:
0.015 A
Supply Current-Max:
0.04 mA
Supply Voltage-Max (Vsup):
3.45 V
Supply Voltage-Min (Vsup):
3.15 V
Supply Voltage-Nom (Vsup):
3.3 V
Surface Mount:
YES
Technology:
CMOS
Temperature Grade:
COMMERCIAL
Terminal Finish:
TIN LEAD
Terminal Form:
BALL
Terminal Pitch:
1 mm
Terminal Position:
BOTTOM
Time@Peak Reflow Temperature-Max (s):
30
Width:
13 mm
72V3640L6BB Frequently Asked Questions (FAQs)
Renesas provides a recommended PCB layout guide in their application note (APL-AN-114) for the 72V3640L6BB. It suggests using a 4-layer PCB with a thermal relief pattern on the top layer, and a solid ground plane on the bottom layer to minimize thermal resistance.
To ensure reliable operation in high-temperature environments, it's essential to follow Renesas' recommended thermal design guidelines, including using a heat sink, thermal interface material, and ensuring good airflow. Additionally, consider using a thermistor or temperature sensor to monitor the device temperature and implement thermal protection mechanisms.
The input capacitor should be a low-ESR, high-frequency capacitor (e.g., ceramic or film capacitor) with a minimum capacitance of 10uF and a voltage rating of at least 100V. The capacitor should be placed as close as possible to the VIN pin to minimize inductance and ensure stable operation.
To optimize the output filter design, use a combination of capacitors and inductors with low ESR and ESL values. A recommended configuration is a 10uF ceramic capacitor in parallel with a 1uF film capacitor, and a 1uH inductor with a low DCR value. Additionally, consider using a shielded inductor and placing the output filter components close to the output pins to minimize noise and ripple.
The bootstrap capacitor should be a low-ESR, high-frequency capacitor (e.g., ceramic or film capacitor) with a minimum capacitance of 1uF and a voltage rating of at least 25V. The capacitor should be placed as close as possible to the BOOT pin to ensure proper operation of the high-side switch.
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72V3640L6BB Overview
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