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Image	Part Number	D.S	Description	Package Category	Prices / Stock	Model	Action
	AL460A-7-PBF AverLogic	1	AverLogic AL460A-7-PBF, FIFO Memory, Single 128Mbit, 8M x 16, Uni-Directional 105MHz, 2.5 → 3.3 V, 128-Pin LQFP	Quad Flat Packages	AL460A-7-PBF	3D model available Symbol and footprint available 3	1 Download Model
	SN74ACT7811-20PN Texas Instruments	1	IC SYNC FIFO MEM 1024X18 80-LQFP	Quad Flat Packages	SN74ACT7811-20PN	3D model available Symbol and footprint available 3	1 Download Model
	IDT72T36125L5BBI Renesas Electronics	1	IDT IDT72T36125L5BBI, FIFO Memory, Dual, 256K x 36 bit, Uni-Directional 10ns 200MHz, 2.375 → 2.625 V, 240-Pin BGA	BGA	IDT72T36125L5BBI	3D model available Symbol and footprint available 3	1 Download Model
	IDT7206L15JG Renesas Electronics	1	IDT IDT7206L15JG, FIFO Memory, Dual 144kbit, 16K x 9 bit, Bi-Directional 15ns, 4.5 → 5.5 V, 32-Pin PLCC	Plastic Leaded Chip Carrier	IDT7206L15JG	3D model not available Symbol and footprint available 2	1 Download Model

	SN74ACT7805-25DLR Texas Instruments	1	FIFO 256 x 18 synchronous FIFO memory	Small Outline Packages	SN74ACT7805-25DLR	3D model available Symbol and footprint available 3	1 Download Model
	SN74ALS236N Texas Instruments	1	IC MEMORY 64X4 ASYNCH 16-DIP	Dual-In-Line Packages	SN74ALS236N	3D model available Symbol and footprint available 3	1 Download Model
	CD74HC40105M96E4 Texas Instruments	1	Registers 4bits x 16words FIFO	Small Outline Packages	CD74HC40105M96E4	3D model available Symbol and footprint available 3	1 Download Model
	72V3650L7-5BB8 Renesas Electronics	1	The 72V3650 2K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3650L7-5BB8	3D model available Symbol and footprint available 3	1 Download Model
	72V255LA10TFG8 Renesas Electronics	1	The 72V255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72255 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that nee	Quad Flat Packages	72V255LA10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V285L10TFG Renesas Electronics	1	The 72V285 is an 64K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72285 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that ne	Quad Flat Packages	72V285L10TFG	3D model available Symbol and footprint available 3	1 Download Model
	7201LA12SOG Renesas Electronics	1	The 7201 is a 512 x 9 dual-port FIFO memory that loads and empties data on a first-in/first-out basis. The device uses Full and Empty flags to prevent data overflow and underflow. It has a Retransmit (RT) capability that allows for reset of the read pointer to its initial position when RT is pulsed LOW. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7201LA12SOG	3D model available Symbol and footprint available 3	1 Download Model
	72V3642L10PFG8 Renesas Electronics	1	The 72V3642 is a 3.3V version of the 723642. Two independent 1K x 36 dual-port SRAM FIFOs onboard each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	72V3642L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72235LB10TFG8 Renesas Electronics	1	The 72235 is a 2K x 18 First-In, First-Out memory with clocked read and write controls and would be useful for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. These FIFOs have 18-bit input and output ports. The read clock can be tied to the write clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation. These devices are depth expandable using a Daisy-Chain technique	Quad Flat Packages	72235LB10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	723642L15PFG8 Renesas Electronics	1	The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723642L15PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V3680L7-5PFGI8 Renesas Electronics	1	The 72V3680 16K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	Quad Flat Packages	72V3680L7-5PFGI8	3D model available Symbol and footprint available 3	1 Download Model

	72V3670L6BB Renesas Electronics	1	The 72V3670 8K x 36 SuperSync II FIFO memory with clocked read and write controls offers flexible Bus-Matching x36/x18/x9 data flow and Asynchronous/Synchronous translation on the read or write ports ; SuperSync II FIFO's are appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes.	BGA	72V3670L6BB	3D model available Symbol and footprint available 3	1 Download Model
	72V245L15PFGI8 Renesas Electronics	1	The 72V245 is a 4K x 18 first-in, first-out memory with clocked read and write controls. It is a 3.3V version of the 72245 FIFO and is applicable for a wide variety of data buffering needs, such as optical disk controllers, Local Area Networks (LANs), and interprocessor communication. It has 18-bit input and output ports. The Read Clock(RCLK) can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual-clock operation.	Quad Flat Packages	72V245L15PFGI8	3D model available Symbol and footprint available 3	1 Download Model
	7283L15PAGI8 Renesas Electronics	1	The 7283 is a dual-FIFO memory that loads and empties data on a first-in/first-out basis. It utilizes a 9-bit wide data array to allow for control and parity bits at the user's option. This is useful in data communications applications where a parity bit is needed for transmission/reception error checking. It is designed for those applications requiring asynchronous and simultaneous read/writes in multiprocessing and rate buffer applications.	Small Outline Packages	7283L15PAGI8	3D model available Symbol and footprint available 3	1 Download Model
	72V281L10PFG8 Renesas Electronics	1	The 72V281 is a 64K x 9 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72281 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. The period required by the retransmit operation and the first word data latency period is now fixed and short. (The variable clock cycle cou	Quad Flat Packages	72V281L10PFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V851L10TFG8 Renesas Electronics	1	The 72V851is a 8K x 9 dual synchronous FIFO that is functionally equivalent to two 72V251 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V851L10TFG8	3D model available Symbol and footprint available 3	1 Download Model
	72V255LA15PFGI Renesas Electronics	1	The 72V255 is an 8K x 18 SuperSync FIFO memory with clocked read and write controls. It's a functionally compatible version of the 72255 designed to run off a 3.3V supply for very low power consumption. The Frequency Select pin (FS) has been removed, thus it is no longer necessary to select which of the two clock inputs, RCLK or WCLK, is running at the higher frequency. SuperSync FIFOs are particularly appropriate for networking, video, telecommunications, data communications and other applications that nee	Quad Flat Packages	72V255LA15PFGI	3D model available Symbol and footprint available 3	1 Download Model
	72V221L15PFG Renesas Electronics	1	The 72V221 is a 1K x 9 First-In, First-Out memory with clocked read and write controls. It is a 3.3V version of the 72221 device and is applicable for a wide variety of data buffering needs such as graphics, local area networks and interprocessor communication. It has 9-bit input and output ports. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dualclock operation.	Quad Flat Packages	72V221L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	723642L15PFG Renesas Electronics	1	The 723642 is a monolithic Bidirectional SyncFIFO (clocked) memory. Two independent 1K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.	Quad Flat Packages	723642L15PFG	3D model available Symbol and footprint available 3	1 Download Model
	72V841L15TFGI Renesas Electronics	1	The 72V841is a 4K x 9 dual synchronous FIFO that is functionally equivalent to two 72V241 FIFOs in a single package with all associated control, data, and flag lines assigned to separate pins. Each FIFOs has a 9-bit input and output data port. The Read Clock can be tied to the Write Clock for single clock operation or the two clocks can run asynchronous of one another for dual clock operation.	Quad Flat Packages	72V841L15TFGI	3D model available Symbol and footprint available 3	1 Download Model
	72T18105L5BBGI Renesas Electronics	1	The 72T18105 is a 128K x 18 / 256K x 9 TeraSync 2.5V FIFO memory with clocked read and write controls and a flexible Bus-Matching x18/x9 data flow. Bus-Matching TeraSync FIFOs are particularly appropriate for network, video, telecommunications, data communications and other applications that need to buffer large amounts of data and match busses of unequal sizes. There are two possible timing modes of operation with these devices: IDT Standard mode and First Word Fall Through mode.	BGA	72T18105L5BBGI	3D model available Symbol and footprint available 3	1 Download Model
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