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BSS670S2L - Infineon

Description: N-Channel MOSFET Transistor, 540 mA, 55 V, 3-Pin SOT-23 Infineon BSS670S2L

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PCB Footprints
BSS670S2L - Infineon PCB footprint - SOT23 (3-Pin) - SOT23 (3-Pin) - SOT-23
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3D Models
BSS670S2L - Infineon  - 3D model - SOT23 (3-Pin) - SOT-23
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BSS670S2L Details

  • Manufacturer Part Number:

    BSS670S2L

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    SOT-23

  • Pin Count:

    3

  • ECCN Code:

    EAR99

  • Manufacturer:

    Infineon Technologies AG

  • YTEOL:

    6.8

  • Additional Feature:

    LOGIC LEVEL COMPATIBLE

  • Configuration:

    SINGLE WITH BUILT-IN DIODE

  • DS Breakdown Voltage-Min:

    55 V

  • Drain Current-Max (ID):

    0.54 A

  • Drain-source On Resistance-Max:

    0.825 Ω

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • Feedback Cap-Max (Crss):

    10 pF

  • JESD-30 Code:

    R-PDSO-G3

  • JESD-609 Code:

    e3

  • Moisture Sensitivity Level:

    1

  • Number of Elements:

    1

  • Number of Terminals:

    3

  • Operating Mode:

    ENHANCEMENT MODE

  • Operating Temperature-Max:

    150 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE

  • Peak Reflow Temperature (Cel):

    260

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    0.36 W

  • Qualification Status:

    Not Qualified

  • Surface Mount:

    YES

  • Terminal Finish:

    Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Position:

    DUAL

  • Time@Peak Reflow Temperature-Max (s):

    40

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

BSS670S2L Frequently Asked Questions (FAQs)

  • A 2-layer or 4-layer PCB with a solid ground plane and thermal vias is recommended. The device should be placed near a thermal pad or heat sink to ensure good heat dissipation.
  • Ensure proper heat sinking, use a thermal interface material, and follow the recommended PCB layout guidelines. Also, consider derating the device's power handling at high temperatures.
  • The maximum allowed voltage on the gate pin is ±20V, but it's recommended to keep it within ±15V to ensure reliable operation and prevent damage.
  • Yes, but ensure that the device is properly snubbed and the PCB layout is optimized for high-frequency operation. Also, consider the device's switching losses and thermal performance.
  • Use ESD protection devices, such as TVS diodes or ESD arrays, on the input and output pins. Also, follow proper handling and storage procedures to prevent ESD damage.

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BSS670S2L Overview

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