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CS5368-CQZ - Cirrus Logic

Description: Audio A/D Converter ICs 114dB 192kHz 8-Ch ADC w/TDM Interface

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CS5368-CQZ - Cirrus Logic PCB footprint - Quad Flat Packages - Quad Flat Packages - 48L LQFP
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CS5368-CQZ - Cirrus Logic  - 3D model - Quad Flat Packages - 48L LQFP
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CS5368-CQZ Details

  • Manufacturer Part Number:

    CS5368-CQZ

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    QFP

  • Package Description:

    LEAD FREE, MS-026, LQFP-48

  • Pin Count:

    48

  • HTS Code:

    8542.39.00.30

  • Factory Lead Time:

    111 Weeks

  • Manufacturer:

    Cirrus Logic

  • YTEOL:

    0

  • Analog Input Voltage-Max:

    6.24 V

  • Analog Input Voltage-Min:

    5.08 V

  • Converter Type:

    ADC, DELTA-SIGMA

  • JESD-30 Code:

    S-PQFP-G48

  • JESD-609 Code:

    e3

  • Length:

    7 mm

  • Moisture Sensitivity Level:

    3

  • Number of Analog In Channels:

    8

  • Number of Bits:

    24

  • Number of Functions:

    1

  • Number of Terminals:

    48

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Bit Code:

    BINARY

  • Output Format:

    SERIAL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LFQFP

  • Package Equivalence Code:

    QFP48,.35SQ,20

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK, LOW PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    250

  • Qualification Status:

    Not Qualified

  • Sample Rate:

    0.216 MHz

  • Seated Height-Max:

    1.6 mm

  • Supply Voltage-Nom:

    5 V

  • Surface Mount:

    YES

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    MATTE TIN

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Width:

    7 mm

CS5368-CQZ Frequently Asked Questions (FAQs)

  • The recommended power-up sequence is to apply VDD first, followed by VCC, and then the analog power supplies (AVDD and DVDD). This ensures proper device operation and prevents damage.
  • To optimize ADC performance, ensure proper PCB layout, use a low-noise power supply, and optimize the analog input signal conditioning. Additionally, adjust the ADC clock frequency, gain, and offset settings to suit your application's requirements.
  • The maximum allowed input signal amplitude is ±2.5Vpp (peak-to-peak) for the analog input channels. Exceeding this limit may result in signal distortion or device damage.
  • Configure the device by setting the appropriate registers (e.g., ADC_CFG1 and ADC_CFG2) to select the desired input mode. Refer to the datasheet for specific register settings and configuration details.
  • The recommended clock frequency range is 2.4 MHz to 50 MHz. Operating outside this range may affect device performance or result in incorrect data conversion.

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CS5368-CQZ Overview

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