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CS5526-BSZ - Cirrus Logic

Description: Analog to Digital Converters - ADC 20-Bit Delta Sigma Multi-Range ADC

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CS5526-BSZ - Cirrus Logic PCB footprint - Small Outline Packages - Small Outline Packages - 20 PIN SSOP
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CS5526-BSZ - Cirrus Logic  - 3D model - Small Outline Packages - 20 PIN SSOP
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CS5526-BSZ Details

  • Manufacturer Part Number:

    CS5526-BSZ

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    SSOP

  • Package Description:

    0.200 INCH, LEAD FREE, PLASTIC, SSOP-20

  • Pin Count:

    20

  • HTS Code:

    8542.39.00.30

  • Factory Lead Time:

    18 Weeks

  • Manufacturer:

    Cirrus Logic

  • YTEOL:

    0

  • Analog Input Voltage-Max:

    5 V

  • Analog Input Voltage-Min:

    -2.1 V

  • Converter Type:

    ADC, DELTA-SIGMA

  • JESD-30 Code:

    R-PDSO-G20

  • JESD-609 Code:

    e3

  • Length:

    7.2 mm

  • Linearity Error-Max (EL):

    0.0015%

  • Moisture Sensitivity Level:

    3

  • Number of Analog In Channels:

    1

  • Number of Bits:

    20

  • Number of Functions:

    1

  • Number of Terminals:

    20

  • Operating Temperature-Max:

    85 °C

  • Operating Temperature-Min:

    -40 °C

  • Output Bit Code:

    OFFSET BINARY, 2'S COMPLEMENT BINARY

  • Output Format:

    SERIAL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    SSOP

  • Package Equivalence Code:

    SSOP20,.3

  • Package Shape:

    RECTANGULAR

  • Package Style:

    SMALL OUTLINE, SHRINK PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Qualification Status:

    Not Qualified

  • Sample Rate:

    0.05 MHz

  • Seated Height-Max:

    2.13 mm

  • Supply Voltage-Nom:

    5 V

  • Surface Mount:

    YES

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Matte Tin (Sn)

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.65 mm

  • Terminal Position:

    DUAL

  • Width:

    5.3 mm

CS5526-BSZ Frequently Asked Questions (FAQs)

  • The recommended power-up sequence is to apply VCC first, followed by AVCC, and then DVCC. This ensures proper internal biasing and prevents latch-up.
  • To minimize noise and EMI, keep analog and digital traces separate, use a solid ground plane, and place decoupling capacitors close to the device. Also, use a low-ESR capacitor for the AVCC pin.
  • The maximum allowed capacitance for the analog input pins is 10nF. Exceeding this value may affect the device's performance and accuracy.
  • Ensure good airflow around the device, use a heat sink if necessary, and avoid blocking the thermal pad on the bottom of the package. The maximum junction temperature is 150°C.
  • The recommended clock frequency is between 10 kHz and 100 kHz. Operating outside this range may affect the device's performance and accuracy.

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CS5526-BSZ Overview

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