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EP1S20F672I7N - Intel

Description: IC FPGA 426 I/O 672FBGA

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PCB Footprints
EP1S20F672I7N - Intel PCB footprint - BGA - BGA - 672-Pin FineLine Ball-Grid Array (FBGA)_2021
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3D Models
EP1S20F672I7N - Intel  - 3D model - BGA - 672-Pin FineLine Ball-Grid Array (FBGA)_2021
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EP1S20F672I7N Details

  • Manufacturer Part Number:

    EP1S20F672I7N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    35 X 35 MM, 1.27 MM PITCH, LEAD FREE, BGA-672

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • JESD-30 Code:

    S-PBGA-B672

  • JESD-609 Code:

    e1

  • Length:

    27 mm

  • Moisture Sensitivity Level:

    3

  • Number of Inputs:

    426

  • Number of Logic Cells:

    18460

  • Number of Outputs:

    426

  • Number of Terminals:

    672

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    1846 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA672,26X26,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    1.575 V

  • Supply Voltage-Min:

    1.425 V

  • Supply Voltage-Nom:

    1.5 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    27 mm

EP1S20F672I7N Frequently Asked Questions (FAQs)

  • The EP1S20F672I7N has an operating temperature range of 0°C to 85°C (commercial temperature range) and -40°C to 100°C (industrial temperature range).
  • You can implement a clock tree in the EP1S20F672I7N using the Quartus II software, which provides a clock tree synthesis (CTS) tool to optimize clock networks. You can also use the FPGA's dedicated clock networks, such as the global clock network (GCLK) and the regional clock network (RCLK).
  • The maximum frequency achievable with the EP1S20F672I7N depends on the specific design and implementation. However, Intel's Stratix FPGAs are known for their high-performance capabilities, with some devices reaching clock frequencies of up to 1 GHz or more.
  • To optimize power consumption in the EP1S20F672I7N, you can use various techniques such as clock gating, voltage scaling, and dynamic voltage and frequency scaling (DVFS). You can also use the Quartus II software's power analysis and optimization tools to identify and reduce power-hungry areas of your design.
  • The EP1S20F672I7N has a total of 2,048 Kbits of embedded memory, which can be configured as RAM, ROM, or FIFOs. Additionally, the FPGA has 16,640 logic elements (LEs) that can be used to implement user-defined memory structures.

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EP1S20F672I7N Overview

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Part Image EP1S20F672I7 Altera Corporation

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Part Image EP1S20F672I7N Altera Corporation

Field Programmable Gate Array, 18460-Cell, CMOS, PBGA672

Part Image EP1S20F672C7 Altera Corporation

Field Programmable Gate Array, 2132 CLBs, 18460-Cell, CMOS, PBGA672

Part Image EP1S20F672C7N Intel Corporation

Field Programmable Gate Array, 1846 CLBS, 18460-Cell, CMOS, PBGA672

Part Image EP1S20F672I7ES Intel Corporation

Field Programmable Gate Array, 1846 CLBS, CMOS, PBGA672

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