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EP1S25F672C8N - Intel

Description: FPGA Stratix® Family 25660 Cells 357.14MHz 130nm Technology 1.5V 672-Pin FBGA

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EP1S25F672C8N - Intel PCB footprint - BGA - BGA - 672-Pin FineLine BGA
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EP1S25F672C8N - Intel  - 3D model - BGA - 672-Pin FineLine BGA
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EP1S25F672C8N Details

  • Manufacturer Part Number:

    EP1S25F672C8N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    27 X 27 MM, 1 MM PITCH, FBGA-672

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • JESD-30 Code:

    S-PBGA-B672

  • JESD-609 Code:

    e1

  • Length:

    27 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    2852

  • Number of Inputs:

    473

  • Number of Logic Cells:

    25660

  • Number of Outputs:

    473

  • Number of Terminals:

    672

  • Operating Temperature-Max:

    85 °C

  • Organization:

    2566 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA672,26X26,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    1.575 V

  • Supply Voltage-Min:

    1.425 V

  • Supply Voltage-Nom:

    1.5 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    27 mm

EP1S25F672C8N Frequently Asked Questions (FAQs)

  • The EP1S25F672C8N has an operating temperature range of 0°C to 85°C (commercial temperature range) and -40°C to 100°C (industrial temperature range).
  • You can implement a clock tree in the EP1S25F672C8N using the Quartus II software, which provides a clock tree synthesis (CTS) tool to optimize clock networks. You can also use the FPGA's dedicated clock networks, such as the global clock network (GCLK) and the regional clock network (RCLK).
  • The maximum frequency achievable with the EP1S25F672C8N depends on the specific design and the speed grade of the device. However, the maximum clock frequency for this FPGA is typically around 300-400 MHz.
  • You can configure the I/O pins of the EP1S25F672C8N using the Quartus II software, which provides a pin planner tool to assign I/O standards, voltage levels, and other settings to the FPGA's I/O pins.
  • The power consumption of the EP1S25F672C8N depends on the specific design, operating frequency, and voltage supply. However, the typical power consumption of this FPGA is around 1-2 watts, depending on the configuration.

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EP1S25F672C8N Overview

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Part Image EP1S25F672C8 Altera Corporation

Field Programmable Gate Array, 2852 CLBs, 25660-Cell, CMOS, PBGA672

Part Image EP1S25F672C8N Altera Corporation

Field Programmable Gate Array, 2852 CLBs, 25660-Cell, CMOS, PBGA672

Part Image EP1S25F672C8 Intel Corporation

Field Programmable Gate Array, 2566 CLBS, 25660-Cell, CMOS, PBGA672