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EP1SGX10CF672C6N - Intel

Description: StratixGX FPGA Family

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EP1SGX10CF672C6N - Intel - PCB symbol
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EP1SGX10CF672C6N - Intel PCB footprint - BGA - BGA - 672-Pin FineLine BGA
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EP1SGX10CF672C6N - Intel - 3D model - BGA - 672-Pin FineLine BGA
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EP1SGX10CF672C6N Details

  • Manufacturer Part Number:

    EP1SGX10CF672C6N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    27 X 27 MM, 1 MM PITCH, FBGA-672

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Clock Frequency-Max:

    5.37 MHz

  • Combinatorial Delay of a CLB-Max:

    8.245 ns

  • JESD-30 Code:

    S-PBGA-B672

  • JESD-609 Code:

    e1

  • Length:

    27 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    1200

  • Number of Inputs:

    362

  • Number of Logic Cells:

    10570

  • Number of Outputs:

    362

  • Number of Terminals:

    672

  • Operating Temperature-Max:

    85 °C

  • Organization:

    1057 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA672,26X26,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    1.575 V

  • Supply Voltage-Min:

    1.425 V

  • Supply Voltage-Nom:

    1.5 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    27 mm

EP1SGX10CF672C6N Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for EP1SGX10CF672C6N is -40°C to 100°C, with a junction temperature of up to 125°C.
  • Clock management in EP1SGX10CF672C6N can be implemented using the clock management unit (CMU) and the phase-locked loop (PLL) blocks. The CMU generates clock signals for the FPGA fabric, while the PLL blocks generate high-frequency clock signals for the transceivers and other high-speed interfaces.
  • The maximum power consumption of EP1SGX10CF672C6N is approximately 12W, depending on the device configuration, operating frequency, and environmental conditions.
  • Power consumption in EP1SGX10CF672C6N can be optimized by using power-aware design techniques, such as clock gating, voltage scaling, and dynamic voltage and frequency scaling (DVFS). Additionally, Intel's PowerPlay power management technology can be used to reduce power consumption during idle periods.
  • The maximum bandwidth of the transceivers in EP1SGX10CF672C6N is up to 3.2 Gbps, depending on the transceiver type and configuration.

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EP1SGX10CF672C6N Overview

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EP1SGX10CF672C6N Alternates

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Image Part Number Model
Part Image EP1SGX10CF672C6N Altera Corporation

Field Programmable Gate Array, 1200 CLBs, 10570-Cell, CMOS, PBGA672
Part Image EP1SGX10CF672C6 Altera Corporation

Field Programmable Gate Array, 1200 CLBs, 10570-Cell, CMOS, PBGA672
Part Image EP1SGX10CF672I6ES Intel Corporation

Field Programmable Gate Array, 1057 CLBS, 5.37MHz, 10570-Cell, CMOS, PBGA672
Part Image EP1SGX10CF672I6N Intel Corporation

Field Programmable Gate Array, 1057 CLBS, 5.37MHz, 10570-Cell, CMOS, PBGA672
Part Image EP1SGX10CF672I6ES Altera Corporation

Field Programmable Gate Array, CMOS, PBGA672
For a full list of alternate parts for EP1SGX10CF672C6N, check out Findchips.com