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EP2C35F672I8N - Intel

Description: Altera EP2C35F672I8N, FPGA Field Programmable Gate Array Cyclone II 33216 Cells, 33216 Blocks, 1.15 → 1.25 V

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EP2C35F672I8N - Intel PCB footprint - BGA - BGA - 672-Pin FineLine BGA Package, Option 3 – Wirebond
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3D Models
EP2C35F672I8N - Intel  - 3D model - BGA - 672-Pin FineLine BGA Package, Option 3 – Wirebond
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EP2C35F672I8N Details

  • Manufacturer Part Number:

    EP2C35F672I8N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Transferred

  • Package Description:

    LEAD FREE, FBGA-672

  • Country Of Origin:

    Mainland China, Malaysia, Taiwan, USA, Vietnam

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    10

  • Additional Feature:

    ALSO REQUIRES 3.3 SUPPLY

  • Clock Frequency-Max:

    402.5 MHz

  • JESD-30 Code:

    S-PBGA-B672

  • JESD-609 Code:

    e1

  • Length:

    27 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    2076

  • Number of Inputs:

    475

  • Number of Logic Cells:

    33216

  • Number of Outputs:

    459

  • Number of Terminals:

    672

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    2076 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA672,26X26,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    2.6 mm

  • Supply Voltage-Max:

    1.25 V

  • Supply Voltage-Min:

    1.15 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 90 nm

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    27 mm

EP2C35F672I8N Frequently Asked Questions (FAQs)

  • The maximum operating temperature range for the EP2C35F672I8N is -40°C to 100°C.
  • To implement a clock tree in the EP2C35F672I8N, use the Clock Control Block (CCB) to generate a clock signal, and then use the clock network to distribute the clock signal to the various components of the design.
  • The maximum frequency supported by the EP2C35F672I8N is 350 MHz.
  • To optimize power consumption in the EP2C35F672I8N, use the PowerPlay power management technology, which allows you to dynamically adjust the voltage and frequency of the device to reduce power consumption.
  • The EP2C35F672I8N has a total of 33,216 logic elements (LEs) available.

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EP2C35F672I8N Overview

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Image Part Number Model
Part Image EP2C35F672I8 Altera Corporation

Field Programmable Gate Array, 2076 CLBs, 402.5MHz, 33216-Cell, CMOS, PBGA672

Part Image EP2C35F672C8N Intel Corporation

Field Programmable Gate Array, 2076 CLBs, 402.5MHz, 33216-Cell, CMOS, PBGA672