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EP2SGX30DF780C3N - Intel

Description: FPGA, STRATIX II GX

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EP2SGX30DF780C3N - Intel PCB footprint - BGA - BGA - 780-Pin FineLine Ball-Grid Array (FBGA)
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EP2SGX30DF780C3N - Intel  - 3D model - BGA - 780-Pin FineLine Ball-Grid Array (FBGA)
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EP2SGX30DF780C3N Details

  • Manufacturer Part Number:

    EP2SGX30DF780C3N

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Package Description:

    29 X 29 MM, 1 MM PITCH, LEAD FREE, MS-034AAM-1, FBGA-780

  • HTS Code:

    8542.31.00.60

  • Manufacturer:

    Intel Corporation

  • YTEOL:

    0

  • Clock Frequency-Max:

    717 MHz

  • Combinatorial Delay of a CLB-Max:

    4.45 ns

  • JESD-30 Code:

    S-PBGA-B780

  • JESD-609 Code:

    e1

  • Length:

    29 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    33880

  • Number of Inputs:

    361

  • Number of Logic Cells:

    33880

  • Number of Outputs:

    361

  • Number of Terminals:

    780

  • Operating Temperature-Max:

    85 °C

  • Organization:

    33880 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    BGA

  • Package Equivalence Code:

    BGA780,28X28,40

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    3.5 mm

  • Supply Voltage-Max:

    1.25 V

  • Supply Voltage-Min:

    1.15 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS, 90 nm

  • Temperature Grade:

    OTHER

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    1 mm

  • Terminal Position:

    BOTTOM

  • Width:

    29 mm

EP2SGX30DF780C3N Frequently Asked Questions (FAQs)

  • The maximum power consumption of EP2SGX30DF780C3N is around 12W, but it can vary depending on the specific use case and operating conditions.
  • To optimize the performance of EP2SGX30DF780C3N, you can use Intel's Quartus II software to optimize the design, use pipelining and parallel processing, and minimize the number of clock domains.
  • The maximum operating frequency of EP2SGX30DF780C3N is around 500 MHz, but it can vary depending on the specific use case and operating conditions.
  • To implement a DDR3 memory interface with EP2SGX30DF780C3N, you can use Intel's UniPHY IP core, which provides a DDR3 PHY interface, and follow the guidelines provided in the Intel FPGA IP User Guide.
  • The thermal design power (TDP) of EP2SGX30DF780C3N is around 10W, but it can vary depending on the specific use case and operating conditions.

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EP2SGX30DF780C3N Overview

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Part Image EP2SGX30DF780C3 Altera Corporation

Field Programmable Gate Array, 33880 CLBs, 717MHz, 33880-Cell, CMOS, PBGA780

Part Image EP2SGX30DF780I3N Intel Corporation

Field Programmable Gate Array, 33880 CLBs, 622.08MHz, 33380-Cell, CMOS, PBGA780

Part Image EP2SGX30DF780I3 Intel Corporation

Field Programmable Gate Array, 33880 CLBs, 622.08MHz, 33380-Cell, CMOS, PBGA780

Part Image EP2SGX30DF780C3 Intel Corporation

Field Programmable Gate Array, 33880 CLBs, 717MHz, 33880-Cell, CMOS, PBGA780