SERIES CONNECTED, CENTER TAP, 2 ELEMENTS WITH BUILT-IN DIODE
DS Breakdown Voltage-Min:
30 V
Drain Current-Max (ID):
16 A
Drain-source On Resistance-Max:
0.019 Ω
FET Technology:
HIGH ELECTRON MOBILITY
Feedback Cap-Max (Crss):
8 pF
JESD-30 Code:
R-XUUC-X21
Moisture Sensitivity Level:
1
Number of Elements:
2
Number of Terminals:
21
Operating Mode:
ENHANCEMENT MODE
Operating Temperature-Max:
150 °C
Operating Temperature-Min:
-40 °C
Package Body Material:
UNSPECIFIED
Package Shape:
RECTANGULAR
Package Style:
UNCASED CHIP
Polarity/Channel Type:
N-CHANNEL
Pulsed Drain Current-Max (IDM):
50 A
Surface Mount:
YES
Terminal Form:
UNSPECIFIED
Terminal Position:
UPPER
Transistor Application:
SWITCHING
Transistor Element Material:
GALLIUM NITRIDE
EPC2111 Frequently Asked Questions (FAQs)
A good PCB layout for the EPC2111 involves keeping the high-frequency switching node (SW) away from sensitive analog nodes, using a solid ground plane, and minimizing the length of the power loops. A 4-layer PCB with a dedicated power plane and a solid ground plane is recommended.
To ensure the EPC2111 operates within its SOA, monitor the drain-source voltage (Vds), drain current (Id), and junction temperature (Tj). Keep Vds below 100V, Id below 30A, and Tj below 150°C. Use the thermal resistance (Rth) and power dissipation (PD) to estimate Tj.
The recommended gate drive voltage for the EPC2111 is between 5V and 10V. A higher gate drive voltage can reduce switching losses, but may also increase gate charge and reduce reliability.
To minimize EMI, use a shielded layout, keep the switching node (SW) away from sensitive nodes, and use a common-mode choke or ferrite bead on the input and output lines. Also, consider using a spread-spectrum clock or frequency hopping to reduce EMI.
The maximum allowed dv/dt for the EPC2111 is 50V/ns. Exceeding this limit can cause the device to malfunction or fail.
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EPC2111 Overview
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