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FCPF1300N80ZYD - onsemi

Description: 100% Avalanche Tested; ESD Improved Capability; RoHS Compliant; Low Eoss (Typ. 1.57 uJ @ 400V); RDS(on) = 1.05 Ω(Typ.); Low Effective Output Capacitance (Typ. Coss(eff.) = 48.7 pF); Ultra Low Gate Charge (Typ. Qg = 16.2 nC)

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PCB Footprints
FCPF1300N80ZYD - onsemi PCB footprint - Other - Other - TO−220−3LD LF CASE 340BJ ISSUE O
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3D Models
FCPF1300N80ZYD - onsemi  - 3D model - Other - TO−220−3LD LF CASE 340BJ ISSUE O
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FCPF1300N80ZYD Details

  • Manufacturer Part Number:

    FCPF1300N80ZYD

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    TO-220-3

  • Package Description:

    TO-220, 3 PIN

  • Manufacturer Package Code:

    340BJ

  • Country Of Origin:

    Mainland China

  • ECCN Code:

    EAR99

  • Manufacturer:

    onsemi

  • YTEOL:

    0

  • Configuration:

    SINGLE

  • Drain Current-Max (ID):

    4 A

  • FET Technology:

    METAL-OXIDE SEMICONDUCTOR

  • JESD-609 Code:

    e3

  • Number of Elements:

    1

  • Operating Temperature-Max:

    150 °C

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    24 W

  • Surface Mount:

    NO

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

FCPF1300N80ZYD Frequently Asked Questions (FAQs)

  • The recommended PCB layout for optimal thermal performance involves using a minimum of 2 oz copper thickness, a thermal relief pattern under the device, and a solid copper pour on the top and bottom layers. Additionally, it is recommended to use vias to connect the thermal pad to the thermal relief pattern.
  • To ensure reliable operation at high temperatures, it is essential to follow the recommended thermal design guidelines, including using a heat sink, ensuring good thermal interface material (TIM) between the device and heat sink, and keeping the junction temperature (Tj) below the maximum rated value of 150°C.
  • The maximum allowed voltage imbalance between the drain and source pins is ±10V. Exceeding this limit can cause damage to the device.
  • Yes, the FCPF1300N80ZYD can be used in a parallel configuration to increase current handling. However, it is essential to ensure that the devices are properly matched, and the gate drive and layout are designed to minimize current imbalance and oscillations.
  • The recommended gate drive voltage is 10-15V, and the recommended gate drive current is 1-2A. This ensures optimal switching performance and minimizes switching losses.

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FCPF1300N80ZYD Overview

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