Description:Max rDS(on) = 21 mΩ at VGS = -2.5 V, ID = -8.9 A ; Max rDS(on) = 16 mΩ at VGS = -4.5 V, ID = -10 A ; Low profile - 0.8 mm maximum - in the new package MicroFET 2X2 mm ; RoHS Compliant ; Max rDS(on) = 82 mΩ at VGS = -1.8 V, ID = -4.5 A ; Free from halogenated compounds and antimony oxides
A good PCB layout for the FDMA905P involves keeping the input and output traces as short as possible, using a solid ground plane, and minimizing the distance between the device and the antenna. A 4-layer PCB with a dedicated ground plane is recommended.
The FDMA905P requires a stable voltage supply of 2.7V to 5.5V. Ensure that the voltage regulator is capable of providing a clean and stable output, and that the decoupling capacitors are placed close to the device. A 10uF capacitor in parallel with a 100nF capacitor is recommended for decoupling.
The maximum transmit power of the FDMA905P is +20dBm. However, the actual transmit power may vary depending on the antenna design, PCB layout, and operating frequency.
The FDMA905P has a shutdown pin (SHDN) that can be used to put the device in a low-power mode. When the SHDN pin is pulled low, the device enters a low-power state, reducing the current consumption to less than 1uA.
A quarter-wavelength monopole antenna or a dipole antenna with a length of approximately 1/4 wavelength is recommended for optimal performance with the FDMA905P. The antenna should be matched to the device's output impedance of 50 ohms.
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FDMA905P Overview
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