Description:RoHS Compliant ; MSL1 robust package design ; Shielded Gate MOSFET Technology ; Advanced Package and Silicon combination for low rDS(on) and high efficiency ; Max rDS(on) = 4.85 mΩ at VGS = 10 V, ID = 16 A ; Max rDS(on) = 7.8 mΩ at VGS = 6 V, ID = 13 A ; 100% UIL tested
A good PCB layout for the FDMS86150 involves keeping the high-frequency switching nodes (e.g., drain and source) away from sensitive analog nodes, using a solid ground plane, and minimizing loop areas in the power stage. A 4-layer PCB with a dedicated power plane and a solid ground plane is recommended.
To optimize the gate drive circuit, ensure the gate drive voltage is within the recommended range (typically 10-15V), use a low-impedance gate drive circuit, and add a gate resistor (e.g., 10-20 ohms) to dampen ringing. Also, consider using a gate drive IC or a dedicated gate driver chip.
The maximum allowed junction temperature for the FDMS86150 is 150°C. However, it's recommended to keep the junction temperature below 125°C for reliable operation and to prevent thermal runaway.
Use a voltage supervisor or a voltage monitor IC to detect overvoltage and undervoltage conditions. Add a voltage clamp or a TVS diode to protect the device from voltage spikes. Also, consider using a fuse or a PPTC resettable fuse to protect against overcurrent conditions.
Use a heat sink with a thermal resistance of less than 10°C/W, and apply a thermal interface material (TIM) with a thermal conductivity of at least 5 W/m-K. Ensure good airflow around the heat sink, and consider using a fan or a heat pipe for high-power applications.
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FDMS86150 Overview
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