Infineon provides a recommended PCB layout in the application note AN2019-01, which includes guidelines for thermal vias, copper thickness, and component placement to minimize thermal resistance.
Infineon recommends using a heat sink with a thermal interface material (TIM) and ensuring good airflow around the device. The thermal resistance of the heat sink and TIM should be considered in the thermal design.
According to Infineon's application note AN2019-01, the maximum allowed voltage transient on the drain-source voltage (VDS) pin is 50 V for a duration of 10 ms, with a maximum di/dt of 10 A/μs.
Infineon recommends following standard ESD protection procedures, such as using ESD-safe handling and storage, and incorporating ESD protection devices (e.g., TVS diodes) in the circuit design.
Infineon recommends a gate drive voltage of 10-15 V and a current of 1-2 A for optimal switching performance. The gate drive circuit should be designed to provide a fast rise and fall time (typically <10 ns) to minimize switching losses.
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FZ800R45KL3_B5 Overview
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