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ICE40LP1K-CM36A - Lattice Semiconductor

Description: iCE40 LP/HX/LM - Low-power, high-performance FPGA

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ICE40LP1K-CM36A - Lattice Semiconductor - PCB symbol
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PCB Footprints
ICE40LP1K-CM36A - Lattice Semiconductor PCB footprint - BGA - BGA - 36-Ball ucBGA
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3D Models
ICE40LP1K-CM36A - Lattice Semiconductor - 3D model - BGA - 36-Ball ucBGA
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ICE40LP1K-CM36A Details

  • Manufacturer Part Number:

    ICE40LP1K-CM36A

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    8

  • Clock Frequency-Max:

    179.21 MHz

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-PBGA-B36

  • Length:

    2.5 mm

  • Number of CLBs:

    160

  • Number of Inputs:

    25

  • Number of Logic Cells:

    1280

  • Number of Outputs:

    25

  • Number of Terminals:

    36

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    160 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA36,6X6,16

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Packing Method:

    TRAY

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    0.91 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    BOTTOM

  • Width:

    2.5 mm

ICE40LP1K-CM36A Frequently Asked Questions (FAQs)

  • The maximum operating frequency of the ICE40LP1K-CM36A is dependent on the specific application and design. However, the device is typically specified to operate at frequencies up to 200 MHz.
  • To implement a clock domain crossing (CDC) in the ICE40LP1K-CM36A, you can use the built-in CDC primitives or implement a synchronous FIFO to transfer data between clock domains. It's also recommended to use a clock domain crossing module from the Lattice IP library.
  • The power consumption of the ICE40LP1K-CM36A depends on the specific application, operating frequency, and design. However, the typical power consumption is around 100-200 mW at 1.2V and 100 MHz.
  • To configure the ICE40LP1K-CM36A for a specific application, you can use the Lattice Diamond software to create a design, synthesize, and implement the design on the FPGA. You can also use the Lattice iCEcube2 software for programming and debugging.
  • The ICE40LP1K-CM36A has 1280 Kbits of block RAM and 64 Kbits of distributed RAM, for a total of 1344 Kbits of on-chip memory.

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ICE40LP1K-CM36A Overview

Use the download button to access the ICE40LP1K-CM36A schematic symbol, PCB footprint, and 3D model.
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