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ICE40LP1K-CM49TR - Lattice Semiconductor

Description: FPGA - Field Programmable Gate Array iCE40LP 1280 LUTs 1.2V Ultra Low-Power

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PCB Footprints
ICE40LP1K-CM49TR - Lattice Semiconductor PCB footprint - BGA - BGA - 49-Pin UCBGA_2021
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3D Models
ICE40LP1K-CM49TR - Lattice Semiconductor  - 3D model - BGA - 49-Pin UCBGA_2021
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ICE40LP1K-CM49TR Details

  • Manufacturer Part Number:

    ICE40LP1K-CM49TR

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    8

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-PBGA-B49

  • JESD-609 Code:

    e1

  • Length:

    3 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    160

  • Number of Inputs:

    35

  • Number of Logic Cells:

    1280

  • Number of Outputs:

    35

  • Number of Terminals:

    49

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    160 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    3 mm

ICE40LP1K-CM49TR Frequently Asked Questions (FAQs)

  • The maximum operating frequency of the ICE40LP1K-CM49TR is dependent on the specific design and implementation. However, the device is typically capable of operating at frequencies up to 200 MHz.
  • Lattice provides a Clock Domain Crossing (CDC) IP core that can be used to implement CDC in the ICE40LP1K-CM49TR. Additionally, the device's built-in FIFO and synchronization primitives can also be used to implement CDC.
  • The power consumption of the ICE40LP1K-CM49TR depends on the specific design, operating frequency, and usage of the device. However, the typical static power consumption is around 50-100 mW, and the dynamic power consumption can range from 100-500 mW depending on the design.
  • The ICE40LP1K-CM49TR is not specifically designed or qualified for radiation-hardened applications. However, Lattice does offer radiation-hardened FPGAs, such as the RHINO and ECP5U devices, which are designed for use in harsh environments.
  • The ICE40LP1K-CM49TR has built-in security features, including a secure boot mechanism and encryption capabilities. Additionally, Lattice provides a range of security IP cores and tools, such as the Lattice Secure Control (LSC) and the Lattice Encryption and Authentication (LEA) IP cores, to help secure designs.

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ICE40LP1K-CM49TR Overview

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