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ICE40LP4K-CM121 - Lattice Semiconductor

Description: iCE40LP4K-CM121, FPGA iCE40 LP 3520 Cells, 80kbit, 440 Blocks, 1.14 → 1.26 V 121-Pin UCBGA

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PCB Footprints
ICE40LP4K-CM121 - Lattice Semiconductor PCB footprint - BGA - BGA - 121-UCBGA (5x5)
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3D Models
ICE40LP4K-CM121 - Lattice Semiconductor  - 3D model - BGA - 121-UCBGA (5x5)
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ICE40LP4K-CM121 Details

  • Manufacturer Part Number:

    ICE40LP4K-CM121

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    7.6

  • Clock Frequency-Max:

    133 MHz

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-PBGA-B121

  • JESD-609 Code:

    e1

  • Length:

    5 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    440

  • Number of Inputs:

    93

  • Number of Logic Cells:

    3520

  • Number of Outputs:

    93

  • Number of Terminals:

    121

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    440 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA121,11X11,16

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    BOTTOM

  • Width:

    5 mm

ICE40LP4K-CM121 Frequently Asked Questions (FAQs)

  • The maximum clock frequency of the ICE40LP4K-CM121 FPGA is dependent on the specific clock domain and the design implementation. However, the FPGA is capable of supporting clock frequencies up to 300 MHz.
  • The ICE40LP4K-CM121 FPGA does not have a built-in DDR memory interface. However, you can implement a DDR memory interface using the FPGA's I/O pins and a soft DDR controller IP core. Lattice provides a DDR memory interface IP core that can be used for this purpose.
  • No, the ICE40LP4K-CM121 FPGA is not suitable for high-speed serial interfaces like PCIe or SATA. It is a low-power, low-cost FPGA that is better suited for low-speed interfaces like SPI, I2C, and UART.
  • The ICE40LP4K-CM121 FPGA can be programmed using Lattice's iCEcube2 development software. The FPGA can be programmed using a variety of methods, including JTAG, SPI, and I2C.
  • The power consumption of the ICE40LP4K-CM121 FPGA is dependent on the specific design implementation and the operating frequency. However, the FPGA has a typical power consumption of around 100-200 mW at 1.2V and 25°C.

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ICE40LP4K-CM121 Overview

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