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ICE40LP4K-CM121TR - Lattice Semiconductor

Description: FPGA - Field Programmable Gate Array iCE40LM FPGA 3520 Logic Cells

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ICE40LP4K-CM121TR - Lattice Semiconductor PCB footprint - BGA - BGA - 121-UCBGA (5x5)
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3D Models
ICE40LP4K-CM121TR - Lattice Semiconductor  - 3D model - BGA - 121-UCBGA (5x5)
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ICE40LP4K-CM121TR Details

  • Manufacturer Part Number:

    ICE40LP4K-CM121TR

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    7.6

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-PBGA-B121

  • JESD-609 Code:

    e1

  • Length:

    5 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    440

  • Number of Inputs:

    93

  • Number of Logic Cells:

    3520

  • Number of Outputs:

    93

  • Number of Terminals:

    121

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    440 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA121,11X11,16

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    BOTTOM

  • Width:

    5 mm

ICE40LP4K-CM121TR Frequently Asked Questions (FAQs)

  • The maximum operating frequency of the ICE40LP4K-CM121TR is dependent on the specific design and implementation, but it can operate up to 200 MHz.
  • Lattice provides a CDC IP core that can be used to implement clock domain crossing in the ICE40LP4K-CM121TR. Additionally, designers can use synchronization registers or FIFOs to implement CDC.
  • The power consumption of the ICE40LP4K-CM121TR depends on the specific design, operating frequency, and voltage. However, the typical static power consumption is around 50-100 mW, and the dynamic power consumption is around 100-200 mW at 100 MHz.
  • No, the ICE40LP4K-CM121TR is not suitable for high-speed interfaces like PCIe or SATA due to its limited transceiver bandwidth and lack of high-speed serial interface capabilities.
  • The ICE40LP4K-CM121TR can be programmed using Lattice's iCEcube2 software, which provides a comprehensive development environment for designing, implementing, and testing FPGA designs.

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ICE40LP4K-CM121TR Overview

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Part Image ICE40LP4K-CM121 Lattice Semiconductor Corporation

Field Programmable Gate Array, 440 CLBS, 133MHz, 3520-Cell, CMOS, PBGA121