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ICE40LP4K-CM81 - Lattice Semiconductor

Description: series Field Programmable Gate Array (FPGA) IC 63 81920 3520 81-VFBGA

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ICE40LP4K-CM81 - Lattice Semiconductor PCB footprint - BGA - BGA - 81-Ball ucBGA Package
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ICE40LP4K-CM81 - Lattice Semiconductor  - 3D model - BGA - 81-Ball ucBGA Package
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ICE40LP4K-CM81 Details

  • Manufacturer Part Number:

    ICE40LP4K-CM81

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    7.6

  • Clock Frequency-Max:

    133 MHz

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-PBGA-B81

  • JESD-609 Code:

    e1

  • Length:

    4 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    440

  • Number of Inputs:

    63

  • Number of Logic Cells:

    3520

  • Number of Outputs:

    63

  • Number of Terminals:

    81

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    440 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA81,9X9,16

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    4 mm

ICE40LP4K-CM81 Frequently Asked Questions (FAQs)

  • The maximum clock frequency of the ICE40LP4K-CM81 is 275 MHz, but this can vary depending on the specific design and implementation.
  • The ICE40LP4K-CM81 has a dedicated DDR3 memory interface, and Lattice provides a DDR3 IP core that can be used to implement a DDR3 memory interface. The IP core is available in the Lattice IPexpress tool.
  • No, the ICE40LP4K-CM81 is not suitable for high-speed serial interfaces like PCIe or SATA. It is primarily designed for low-power, low-cost applications with slower I/O speeds.
  • The ICE40LP4K-CM81 can be programmed using the Lattice iCEcube2 design software, which includes a synthesizer, placer, and router. The device can be programmed using a JTAG interface or a SPI flash interface.
  • The power consumption of the ICE40LP4K-CM81 depends on the specific design and implementation, but it is typically in the range of 100-500 mW. Power consumption can be reduced by using power-saving features like clock gating, voltage scaling, and dynamic voltage and frequency scaling.

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ICE40LP4K-CM81 Overview

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Part Image ICE40LP4K-CM81TR Lattice Semiconductor Corporation

Field Programmable Gate Array, 440 CLBS, 3520-Cell, CMOS, PBGA81