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iCE40LP8K-CM121 - Lattice Semiconductor

Description: FPGA - Field Programmable Gate Array iCE40LP 7680 LUTs 1.2V Ultra Low-Power

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Symbol
iCE40LP8K-CM121 - Lattice Semiconductor - PCB symbol
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PCB Footprints
iCE40LP8K-CM121 - Lattice Semiconductor PCB footprint - BGA - BGA - ucbga121
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3D Models
iCE40LP8K-CM121 - Lattice Semiconductor - 3D model - BGA - ucbga121
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iCE40LP8K-CM121 Details

  • Manufacturer Part Number:

    ICE40LP8K-CM121

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    7.6

  • Clock Frequency-Max:

    133 MHz

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-PBGA-B121

  • JESD-609 Code:

    e1

  • Length:

    5 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    960

  • Number of Inputs:

    93

  • Number of Logic Cells:

    7680

  • Number of Outputs:

    93

  • Number of Terminals:

    121

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    960 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA121,11X11,16

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    5 mm

iCE40LP8K-CM121 Frequently Asked Questions (FAQs)

  • Lattice provides a PCB design guide that includes layout and routing guidelines for the ICE40LP8K-CM121. It's recommended to follow these guidelines to ensure signal integrity and minimize noise.
  • Lattice provides a CDC design guide that includes guidelines and IP cores for implementing clock domain crossings in the ICE40LP8K-CM121. It's recommended to use these resources to ensure proper CDC implementation.
  • The power consumption of the ICE40LP8K-CM121 depends on the design and usage. Lattice provides a power estimation tool that can help estimate power consumption. To optimize power consumption, consider using low-power modes, clock gating, and dynamic voltage and frequency scaling.
  • Lattice provides a secure boot process guide that includes guidelines and IP cores for implementing a secure boot process in the ICE40LP8K-CM121. It's recommended to use these resources to ensure a secure boot process.
  • The ICE40LP8K-CM121 has an operating temperature range of -40°C to 100°C. However, it's recommended to operate the device within a temperature range of 0°C to 85°C for optimal performance and reliability.

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iCE40LP8K-CM121 Overview

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