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ICE40LP8K-CM121TR - Lattice Semiconductor

Description: FPGA iCE40 LP Family 7680 Cells 40nm Technology 1.2V 121-Pin UCBGA T/R

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PCB Footprints
ICE40LP8K-CM121TR - Lattice Semiconductor PCB footprint - BGA - BGA - 121-UCBGA (5x5)
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3D Models
ICE40LP8K-CM121TR - Lattice Semiconductor  - 3D model - BGA - 121-UCBGA (5x5)
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ICE40LP8K-CM121TR Details

  • Manufacturer Part Number:

    ICE40LP8K-CM121TR

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Country Of Origin:

    Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.31.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    7.6

  • Clock Frequency-Max:

    133 MHz

  • Combinatorial Delay of a CLB-Max:

    9.36 ns

  • JESD-30 Code:

    S-PBGA-B121

  • JESD-609 Code:

    e1

  • Length:

    5 mm

  • Moisture Sensitivity Level:

    3

  • Number of CLBs:

    960

  • Number of Inputs:

    93

  • Number of Logic Cells:

    7680

  • Number of Outputs:

    93

  • Number of Terminals:

    121

  • Operating Temperature-Max:

    100 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    960 CLBS

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    VFBGA

  • Package Equivalence Code:

    BGA121,11X11,16

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, VERY THIN PROFILE, FINE PITCH

  • Packing Method:

    TR

  • Peak Reflow Temperature (Cel):

    NOT SPECIFIED

  • Programmable Logic Type:

    FIELD PROGRAMMABLE GATE ARRAY

  • Seated Height-Max:

    1 mm

  • Supply Voltage-Max:

    1.26 V

  • Supply Voltage-Min:

    1.14 V

  • Supply Voltage-Nom:

    1.2 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Temperature Grade:

    INDUSTRIAL

  • Terminal Finish:

    Tin/Silver/Copper (Sn/Ag/Cu)

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.4 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    NOT SPECIFIED

  • Width:

    5 mm

ICE40LP8K-CM121TR Frequently Asked Questions (FAQs)

  • The maximum operating frequency of the ICE40LP8K-CM121TR is dependent on the specific design and implementation. However, the device is typically capable of operating at frequencies up to 200 MHz.
  • Lattice provides a Clock Domain Crossing (CDC) IP core that can be used to implement CDC in the ICE40LP8K-CM121TR. This IP core provides a safe and reliable way to transfer data between different clock domains.
  • The power consumption of the ICE40LP8K-CM121TR depends on the specific design, operating frequency, and usage of the device. However, the typical power consumption is around 100-200 mW.
  • No, the ICE40LP8K-CM121TR is not a radiation-hardened device and is not suitable for use in high-radiation environments. Lattice does offer radiation-hardened FPGAs, such as the RTG4, which are designed for use in space and other high-radiation applications.
  • Lattice provides a DDR3 memory interface IP core that can be used to implement a DDR3 memory interface in the ICE40LP8K-CM121TR. This IP core provides a pre-verified and validated solution for interfacing with DDR3 memory devices.

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ICE40LP8K-CM121TR Overview

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