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IFN860 - InterFET

Description: JFET N-Channel(Dual) -20V Low Noise

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PCB Footprints
IFN860 - InterFET PCB footprint - Other - Other - TO-71_Master_1-18
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3D Models
IFN860 - InterFET  - 3D model - Other - TO-71_Master_1-18
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IFN860 Details

  • Manufacturer Part Number:

    IFN860

  • Part Life Cycle Code:

    Contact Manufacturer

  • ECCN Code:

    EAR99

  • Manufacturer:

    InterFET Corporation

  • Additional Feature:

    LOW NOISE

  • Configuration:

    SEPARATE, 2 ELEMENTS

  • FET Technology:

    JUNCTION

  • Feedback Cap-Max (Crss):

    20 pF

  • JEDEC-95 Code:

    TO-71

  • JESD-30 Code:

    O-MBCY-W6

  • Number of Elements:

    2

  • Number of Terminals:

    6

  • Operating Mode:

    DEPLETION MODE

  • Operating Temperature-Max:

    150 °C

  • Package Body Material:

    METAL

  • Package Shape:

    ROUND

  • Package Style:

    CYLINDRICAL

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    0.4 W

  • Qualification Status:

    Not Qualified

  • Surface Mount:

    NO

  • Terminal Form:

    WIRE

  • Terminal Position:

    BOTTOM

  • Transistor Application:

    AMPLIFIER

  • Transistor Element Material:

    SILICON

IFN860 Frequently Asked Questions (FAQs)

  • A good PCB layout for the IFN860 should ensure that the input and output pins are separated as much as possible to minimize parasitic inductance and capacitance. Additionally, the PCB should have a solid ground plane to reduce noise and electromagnetic interference.
  • The IFN860 has a high power dissipation, so proper thermal management is crucial. This can be achieved by using a heat sink with a thermal conductivity of at least 1 W/m-K, and ensuring good airflow around the device. The PCB should also be designed to dissipate heat efficiently.
  • The recommended input impedance for the IFN860 is 50 ohms, and the recommended output impedance is also 50 ohms. This ensures maximum power transfer and minimizes signal reflections.
  • Yes, the IFN860 can be used in a push-pull configuration to achieve higher output power and improved linearity. However, this requires careful design and layout to ensure that the two devices are properly matched and biased.
  • The IFN860 requires a bias voltage of around 5-6V, and a bias current of around 10-20mA. The bias circuit should be designed to provide a stable voltage and current, and to minimize noise and ripple.

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IFN860 Overview

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