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J113-D74Z - onsemi

Description: These are Pb-Free Devices; Sourced from Process 51

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J113-D74Z - onsemi PCB footprint - Other - Other - J113-D74Z-6
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J113-D74Z Details

  • Manufacturer Part Number:

    J113-D74Z

  • Brand Name:

    onsemi

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    TO-92-3 LF

  • Manufacturer Package Code:

    135AR

  • Reach Compliance Code:

    Compliant

  • Country Of Origin:

    Mainland China

  • ECCN Code:

    EAR99

  • Manufacturer:

    onsemi

  • YTEOL:

    6.05

  • Configuration:

    SINGLE

  • Drain-source On Resistance-Max:

    100 Ω

  • FET Technology:

    JUNCTION

  • Feedback Cap-Max (Crss):

    5 pF

  • JEDEC-95 Code:

    TO-92

  • JESD-30 Code:

    O-PBCY-T3

  • JESD-609 Code:

    e3

  • Number of Elements:

    1

  • Number of Terminals:

    3

  • Operating Mode:

    DEPLETION MODE

  • Operating Temperature-Max:

    150 °C

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Shape:

    ROUND

  • Package Style:

    CYLINDRICAL

  • Polarity/Channel Type:

    N-CHANNEL

  • Power Dissipation-Max (Abs):

    0.4 W

  • Qualification Status:

    Not Qualified

  • Surface Mount:

    NO

  • Terminal Finish:

    Matte Tin (Sn) - annealed

  • Terminal Form:

    THROUGH-HOLE

  • Terminal Position:

    BOTTOM

  • Transistor Application:

    SWITCHING

  • Transistor Element Material:

    SILICON

J113-D74Z Frequently Asked Questions (FAQs)

  • The recommended operating temperature range for the J113-D74Z is -40°C to 150°C.
  • To ensure reliability, follow the recommended derating guidelines, use a heat sink if necessary, and ensure good thermal design and layout practices.
  • The maximum allowable power dissipation for the J113-D74Z is 1.5 W at 25°C free-air temperature, and it decreases with increasing temperature.
  • Use proper ESD handling and storage procedures, and consider adding external ESD protection devices if necessary, such as TVS diodes or ESD arrays.
  • Follow good PCB design practices, such as using a solid ground plane, minimizing trace lengths, and using a low-ESR capacitor for decoupling.

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J113-D74Z Overview

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Part Image J112,126 NXP Semiconductors

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Part Image J113D26Z Fairchild Semiconductor Corporation

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Part Image 934005280126 NXP Semiconductors

Small Signal Field-Effect Transistor, 40V, 1-Element, N-Channel, Silicon, Junction FET, TO-92

Part Image J113 Micro Electronics Ltd

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Part Image J113D27Z Fairchild Semiconductor Corporation

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