Part Image

LC4064V-75T100I - Lattice Semiconductor

Description: CPLD ispMACH® 4000V Family 64 Macro Cells 168MHz 3.3V 100-Pin TQFP Tray

Download LC4064V-75T100I Model
Schematic
symbols
Schematic symbol is unavailable for download
PCB
footprints
PCB footprint is unavailable for download
3D
models
3D model is unavailable for download
PCB Footprints
LC4064V-75T100I - Lattice Semiconductor PCB footprint - Quad Flat Packages - Quad Flat Packages - 100-Pin TQFP
click to zoom
3D Models
LC4064V-75T100I - Lattice Semiconductor  - 3D model - Quad Flat Packages - 100-Pin TQFP
click to zoom

LC4064V-75T100I Details

  • Manufacturer Part Number:

    LC4064V-75T100I

  • Pbfree Code:

    No

  • Part Life Cycle Code:

    Obsolete

  • Part Package Code:

    QFP

  • Package Description:

    TQFP-100

  • Pin Count:

    100

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    0

  • Architecture:

    PAD-TYPE

  • Clock Frequency-Max:

    111 MHz

  • In-System Programmable:

    YES

  • JESD-30 Code:

    S-PQFP-G100

  • JESD-609 Code:

    e0

  • JTAG BST:

    YES

  • Length:

    14 mm

  • Moisture Sensitivity Level:

    3

  • Number of Dedicated Inputs:

    10

  • Number of I/O Lines:

    64

  • Number of Inputs:

    74

  • Number of Macro Cells:

    64

  • Number of Outputs:

    64

  • Number of Product Terms:

    83

  • Number of Terminals:

    100

  • Operating Temperature-Max:

    105 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    10 DEDICATED INPUTS, 64 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LFQFP

  • Package Equivalence Code:

    QFP100,.63SQ,20

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK, LOW PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    240

  • Programmable Logic Type:

    EE PLD

  • Propagation Delay:

    7.5 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.6 mm

  • Supply Voltage-Max:

    3.6 V

  • Supply Voltage-Min:

    3 V

  • Supply Voltage-Nom:

    3.3 V

  • Surface Mount:

    YES

  • Terminal Finish:

    TIN LEAD

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    30

  • Width:

    14 mm

LC4064V-75T100I Frequently Asked Questions (FAQs)

  • The recommended operating voltage range for LC4064V-75T100I is 3.3V ± 10%.
  • Lattice recommends using the Clock Tree Synthesis (CTS) tool in the Lattice Diamond software to implement a clock tree in LC4064V-75T100I. The CTS tool helps to optimize clock tree routing for minimal skew and latency.
  • The maximum frequency supported by LC4064V-75T100I is 100 MHz. However, the actual frequency supported may vary depending on the design and operating conditions.
  • The I/O banks in LC4064V-75T100I can be configured using the Lattice Diamond software. The software provides a graphical interface to configure the I/O banks, including setting the voltage, slew rate, and termination.
  • The power consumption of LC4064V-75T100I depends on the design and operating conditions. However, according to the datasheet, the typical static power consumption is around 100 mW, and the dynamic power consumption is around 200 mW at 100 MHz.

Trust Checks

This model has been provided by community users.
Community Provided
This model has been verified by system checks.
System Verified
This model has been reviewed by community users.
Community Approved
Sponsored

LC4064V-75T100I Overview

Use the download button to access the LC4064V-75T100I schematic symbol, PCB footprint, and 3D model.
To find more CAD model downloads similar to this part, try a partial part number search, like LC406, or try a keyword search, such as Programmable Logic Devices

Parts related to LC4064V-75T100I

Showing 0 results