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LC4064V-75TN100I - Lattice Semiconductor

Description: CPLD - Complex Programmable Logic Devices PROGRAMMABLE SUPER FAST HI DENSITY PLD

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LC4064V-75TN100I - Lattice Semiconductor PCB footprint - Quad Flat Packages - Quad Flat Packages - 100-Pin TQFP
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LC4064V-75TN100I - Lattice Semiconductor  - 3D model - Quad Flat Packages - 100-Pin TQFP
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LC4064V-75TN100I Details

  • Manufacturer Part Number:

    LC4064V-75TN100I

  • Pbfree Code:

    Yes

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    QFP

  • Package Description:

    TQFP-100

  • Pin Count:

    100

  • Country Of Origin:

    Indonesia, Malaysia

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    5

  • Architecture:

    PAD-TYPE

  • Clock Frequency-Max:

    111 MHz

  • In-System Programmable:

    YES

  • JESD-30 Code:

    S-PQFP-G100

  • JESD-609 Code:

    e3

  • JTAG BST:

    YES

  • Length:

    14 mm

  • Moisture Sensitivity Level:

    3

  • Number of Dedicated Inputs:

    10

  • Number of I/O Lines:

    64

  • Number of Inputs:

    74

  • Number of Macro Cells:

    64

  • Number of Outputs:

    64

  • Number of Product Terms:

    83

  • Number of Terminals:

    100

  • Operating Temperature-Max:

    105 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    10 DEDICATED INPUTS, 64 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    LFQFP

  • Package Equivalence Code:

    QFP100,.63SQ,20

  • Package Shape:

    SQUARE

  • Package Style:

    FLATPACK, LOW PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    EE PLD

  • Propagation Delay:

    7.5 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.6 mm

  • Supply Voltage-Max:

    3.6 V

  • Supply Voltage-Min:

    3 V

  • Supply Voltage-Nom:

    3.3 V

  • Surface Mount:

    YES

  • Terminal Finish:

    MATTE TIN

  • Terminal Form:

    GULL WING

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    QUAD

  • Time@Peak Reflow Temperature-Max (s):

    40

  • Width:

    14 mm

LC4064V-75TN100I Frequently Asked Questions (FAQs)

  • The recommended operating voltage range for LC4064V-75TN100I is 3.3V ± 10%.
  • To implement a clock tree in LC4064V-75TN100I, use the Global Clock Network (GCN) which provides a low-skew, high-fanout clock distribution network. The GCN is optimized for clock signal distribution and can be used to drive clock signals to multiple locations on the device.
  • The maximum frequency of operation for LC4064V-75TN100I is 75 MHz.
  • To optimize power consumption in LC4064V-75TN100I, use the Power Management features such as clock gating, power gating, and voltage scaling. Additionally, use the Lattice Diamond software to optimize the design for power consumption.
  • The maximum number of user I/Os available in LC4064V-75TN100I is 100.

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