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LC4064ZE-7MN64I - Lattice Semiconductor

Description: LATTICE SEMICONDUCTOR - LC4064ZE-7MN64I - CPLD, 64, 48 I/O's, BGA, 64 Pins, 241 MHz

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LC4064ZE-7MN64I - Lattice Semiconductor PCB footprint - BGA - BGA - 64-Ball csBGA
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LC4064ZE-7MN64I - Lattice Semiconductor  - 3D model - BGA - 64-Ball csBGA
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LC4064ZE-7MN64I Details

  • Manufacturer Part Number:

    LC4064ZE-7MN64I

  • Rohs Code:

    Yes

  • Part Life Cycle Code:

    Active

  • Part Package Code:

    BGA

  • Package Description:

    5 X 5 MM, 0.5 MM PITCH, LEAD FREE, CSBGA-64

  • Pin Count:

    64

  • Country Of Origin:

    Malaysia, Taiwan

  • ECCN Code:

    EAR99

  • HTS Code:

    8542.39.00.01

  • Manufacturer:

    Lattice Semiconductor Corporation

  • YTEOL:

    5

  • Additional Feature:

    YES

  • Clock Frequency-Max:

    111 MHz

  • In-System Programmable:

    YES

  • JESD-30 Code:

    S-PBGA-B64

  • JESD-609 Code:

    e1

  • JTAG BST:

    YES

  • Length:

    5 mm

  • Moisture Sensitivity Level:

    3

  • Number of Dedicated Inputs:

    4

  • Number of I/O Lines:

    48

  • Number of Inputs:

    52

  • Number of Macro Cells:

    64

  • Number of Outputs:

    48

  • Number of Terminals:

    64

  • Operating Temperature-Max:

    105 °C

  • Operating Temperature-Min:

    -40 °C

  • Organization:

    4 DEDICATED INPUTS, 48 I/O

  • Output Function:

    MACROCELL

  • Package Body Material:

    PLASTIC/EPOXY

  • Package Code:

    TFBGA

  • Package Equivalence Code:

    BGA64,8X8,20

  • Package Shape:

    SQUARE

  • Package Style:

    GRID ARRAY, THIN PROFILE, FINE PITCH

  • Peak Reflow Temperature (Cel):

    260

  • Programmable Logic Type:

    EE PLD

  • Propagation Delay:

    7.5 ns

  • Qualification Status:

    Not Qualified

  • Seated Height-Max:

    1.1 mm

  • Supply Voltage-Max:

    1.9 V

  • Supply Voltage-Min:

    1.7 V

  • Supply Voltage-Nom:

    1.8 V

  • Surface Mount:

    YES

  • Technology:

    CMOS

  • Terminal Finish:

    TIN SILVER COPPER

  • Terminal Form:

    BALL

  • Terminal Pitch:

    0.5 mm

  • Terminal Position:

    BOTTOM

  • Time@Peak Reflow Temperature-Max (s):

    40

  • Width:

    5 mm

LC4064ZE-7MN64I Frequently Asked Questions (FAQs)

  • The recommended power-up sequence is to apply VCCIO before VCC. This ensures that the I/O banks are powered up after the core voltage is stable.
  • To implement a CDC, use a synchronizer circuit or a FIFO-based CDC. The synchronizer circuit can be implemented using a double-flop synchronizer or a pulse synchronizer. The FIFO-based CDC uses a FIFO to transfer data between clock domains.
  • The maximum frequency of the LC4064ZE-7MN64I is 150 MHz. However, the actual frequency may vary depending on the design and the operating conditions.
  • To optimize power consumption, use the power management features of the device, such as clock gating, power gating, and dynamic voltage and frequency scaling. Additionally, optimize the design to minimize switching activity and use low-power modes when possible.
  • The maximum current rating of the LC4064ZE-7MN64I is 100 mA per I/O bank. However, the actual current consumption may vary depending on the design and the operating conditions.

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LC4064ZE-7MN64I Overview

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